Semiconductor integrated circuit device

US9455711B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9455711-B2
Application numberUS-201514806940-A
CountryUS
Kind codeB2
Filing dateJul 23, 2015
Priority dateAug 7, 2014
Publication dateSep 27, 2016
Grant dateSep 27, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor integrated circuit device that has a high-voltage analog switch circuit and is operable at a low power-supply voltage, and which has a first high-voltage MOSFET HN 1 , a second high-voltage MOSFET, and a first floating gate voltage control circuit. The first floating gate voltage control circuit operates at a voltage of 5 V or lower, and when turning on the first high-voltage MOSFET and the second high-voltage MOSFET, the first floating gate voltage control circuit sets a voltage in the source terminal of the first high-voltage MOSFET as a reference voltage, adds a floating voltage corresponding to the power-supply voltage to the reference voltage, and supplies the added voltage to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor integrated circuit device, including a high-voltage MOSFET in a semiconductor region arranged on a main surface of a semiconductor substrate via an insulating substrate, the semiconductor integrated circuit device comprising: a first high-voltage MOSFET of a first conductive type having a source terminal, a drain terminal, and a gate terminal; a second high-voltage MOSFET of the first conductive type having a source terminal connected to the source terminal of the first high-voltage MOSFET, a gate terminal connected to the gate terminal of the first high-voltage MOSFET, and a drain terminal; and a first floating gate voltage control circuit configured to operate at a voltage within the range between a voltage exceeding a ground voltage and a voltage of 5 V or lower as a power-supply voltage and control on/off states of the first high-voltage MOSFET and the second high-voltage MOSFET according to a first control signal, the first floating gate voltage control circuit being connected to a source terminal of the first high-voltage MOSFET and a gate terminal of the first high-voltage MOSFET, and when turning on the first high-voltage MOSFET and the second high-voltage MOSFET, the first floating gate voltage control circuit setting a voltage in the source terminal of the first high-voltage MOSFET as a reference voltage, adding a floating voltage corresponding to the power-supply voltage to the reference voltage, and supplying the floating voltage to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET. 2. The semiconductor integrated circuit device according to claim 1 , wherein the first floating gate voltage control circuit includes a latch circuit that holds the voltage to be supplied to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET, a low-voltage MOSFET with a lower withstand voltage than those of the first high-voltage MOSFET and the second high-voltage MOSFET is formed in the semiconductor region arranged on the one main surface of the semiconductor substrate via the insulating substrate, and the ground voltage is supplied to a surface of the semiconductor substrate opposed to the one main surface. 3. The semiconductor integrated circuit device according to claim 2 , comprising a ground voltage clamp circuit that is connected between the ground voltage and the drain terminal of the first high-voltage MOSFET and/or the drain terminal of the second high-voltage MOSFET, wherein the ground voltage clamp circuit includes a third high-voltage MOSFET of the first conductive type that has a drain terminal, a source terminal, and a gate terminal connected to the drain terminal of the first high-voltage MOSFET and/or the drain terminal of the second high-voltage MOSFET, a fourth high-voltage MOSFET of the first conductive type that has a source terminal connected to the source terminal of the third high-voltage MOSFET, a drain terminal connected to the ground voltage, and a gate terminal connected to the gate terminal of the third high-voltage MOSFET, and a second floating gate voltage control circuit configured to operate at a voltage within the range between a voltage exceeding a ground voltage and a voltage of 5 V or lower as a power-supply voltage and control on/off states of the third high-voltage MOSFET and the fourth high-voltage MOSFET, wherein the second floating voltage control circuit is connected to the source terminal of the third high-voltage MOSFET and the gate terminal of the third high-voltage MOSFET, the second floating voltage control circuit sets a voltage in the source terminal of the third high-voltage MOSFET as a reference voltage, and when turning on the third high-voltage MOSFET and the fourth high-voltage MOSFET, the second floating voltage control circuit adds a floating voltage corresponding to the power-supply voltage to the reference voltage, and supplies the floating voltage to the gate terminals of the third high-voltage MOSFET and the fourth high-voltage MOSFET. 4. The semiconductor integrated circuit device according to claim 3 , wherein the ground voltage clamp circuit includes a low-voltage MOSFET of the first conductive type that has a drain terminal connected to the drain terminal of the fourth high-voltage MOSFET, a source terminal connected to the ground voltage, and a gate terminal, and a second control signal with one signal voltage corresponding to the power-supply voltage and the other signal voltage corresponding to the ground voltage is supplied to the gate terminal of the low-voltage MOSFET to control the low-voltage MOSFET to turn on in synchronization with the third high-voltage MOSFET and the fourth high-voltage MOSFET. 5. The semiconductor integrated circuit device according to claim 4 , wherein the ground voltage clamp circuit includes a diode that is connected between the source terminal and the drain terminal of the low-voltage MOSFET, and forms a bidirectional diode in conjunction with a body diode formed between the drain terminal of the low-voltage MOSFET and the semiconductor region in which the low-voltage MOSFET is formed, and a resistor connected between the drain terminal and the source terminal of the low-voltage MOSFET. 6. The semiconductor integrated circuit device according to claim 3 , comprising: one or more channels; and a logical control circuit configured to operate at a voltage within the range between a voltage exceeding a ground voltage and a voltage of 5 V or lower as a power-supply voltage and supply a third control signal to the one or more channels, wherein the one or more channels include the first high-voltage MOSFET, the second high-voltage MOSFET, the first floating gate voltage control circuit, and the ground voltage clamp circuit, the first control signal is generated at the first floating gate voltage control circuit according to the third control signal from the logical control circuit, and on/off states of the third high-voltage MOSFET and the fourth high-voltage MOSFET at the ground voltage clamp circuit are controlled by the third control signal. 7. The semiconductor integrated circuit device according to claim 4 , comprising: one or more channels; and a logical control circuit configured to operate at a voltage within the range between a voltage exceeding a ground voltage and a voltage of 5 V or lower as a power-supply voltage and supply a third control signal to the one or more channels, wherein the one or more channels include the first high-voltage MOSFET, the second high-voltage MOSFET, the first floating gate voltage control circuit, and the ground voltage clamp circuit, the first control signal is generated at the first floating gate voltage control circuit according to the third control signal from the logical control circuit, and on/off states of the third high-voltage MOSFET and the fourth high-voltage MOSFET at the ground voltage clamp circuit are controlled by the third control signal. 8. The semiconductor integrated circuit device according to claim 5 , comprising: one or more channels; and a logical control circuit configured to operate at a voltage within the range between a voltage exceeding a ground voltage and a voltage of 5 V or lower as a power-supply voltage and supply a third control signal to the one or more channels, wherein the one or more channels include the first high-voltage MOSFET, the second high-voltage MOSFET, the first floating gate voltage control circuit, and the ground voltage clamp circuit, the first control signal is generated at the first floating gate voltage control circuit according to the third control signal from the logical control circuit, and on/off states of the third high

Assignees

Inventors

Classifications

  • modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal · CPC title

  • in a symmetrical configuration · CPC title

  • Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title

  • by using a control or a clock signal, e.g. in order to apply power supply · CPC title

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Frequently asked questions

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What does patent US9455711B2 cover?
A semiconductor integrated circuit device that has a high-voltage analog switch circuit and is operable at a low power-supply voltage, and which has a first high-voltage MOSFET HN 1 , a second high-voltage MOSFET, and a first floating gate voltage control circuit. The first floating gate voltage control circuit operates at a voltage of 5 V or lower, and when turning on the first high-voltage MO…
Who is the assignee on this patent?
Hitachi Ltd
What technology area does this patent fall under?
Primary CPC classification H03K19/0016. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 27 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).