Driver circuit with gate clamp supporting stress testing

Patent metadata

Field	Value
Publication number	US-9331672-B2
Application number	US-201414449232-A
Country	US
Kind code	B2
Filing date	Aug 1, 2014
Priority date	Jun 30, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

First claim

What is claimed is:

1. A circuit, comprising:
a generator circuit configured to receive a reference voltage at a reference node and output a control signal for application to a gate terminal of a power transistor;
a first current source configured to generate a first current for application to said reference node;
a second current source configured to generate a second current;
a switching circuit configured to selectively couple the second current to said reference node in response to a gate stress test enable signal;
a first resistor coupled between the reference node and a drive node of the power transistor across which the reference voltage is generated;
wherein said reference voltage is variable having a lower value as a function of the first current when stress test is not enabled and having a higher value as a function of the first and second currents when gate stress test is enabled; and
a clamp circuit coupled between said reference node and the gate terminal of the power transistor and configured to apply a clamp voltage as a function of the reference voltage.

2. The circuit of claim 1 , further comprising said power transistor with the gate terminal and a source-drain path coupled to said drive node.

3. The circuit of claim 1 , wherein said clamp circuit comprises:
a first transistor;
a second transistor;
wherein source-drain paths of said first and second transistors are coupled in series between said reference node and the gate terminal of the power transistor.

4. The circuit of claim 3 , wherein said clamp circuit further comprises:
a gate terminal of the first transistor coupled to the gate terminal of the power transistor; and
a gate terminal of the second transistor coupled to an intermediate node at a series coupling point of the first and second transistors.

5. The circuit of claim 4 , wherein the clamp circuit further comprises a third transistor coupled with the second transistor to form a current mirroring circuit.

6. The circuit of claim 5 , wherein the clamp circuit further comprises a second resistor coupled in series with a source-drain path of the third transistor between the gate terminal of the power transistor and the drive node.

7. The circuit of claim 6 , wherein the clamp circuit further comprises a fourth transistor having a source-drain path coupled between the gate terminal of the power transistor and the drive node and a gate terminal coupled to said second resistor.

8. The circuit of claim 1 , wherein said generator circuit is configured to generate the control signal for application to the gate terminal of the power transistor in response to an input signal.

9. The circuit of claim 1 , wherein said generator circuit is further configured to disconnect from the gate terminal of the power transistor when stress test is enabled.

10. The circuit of claim 1 , wherein the clamp voltage is lower when stress test is not enabled and higher when gate stress test is enabled.

11. A circuit, comprising:
a generator circuit configured to receive a reference voltage at a reference node and output a control signal for application to a gate terminal of a power transistor configured to drive an output node;
a first transistor;
a second transistor;
wherein source-drain paths of said first and second transistors are coupled in series between said reference node and the gate terminal of the power transistor;
a third transistor coupled with the second transistor to form a current mirroring circuit; and
a fourth transistor having a source-drain path coupled between the gate terminal of the power transistor and the output node and a gate terminal coupled to an output of the current mirroring circuit.

12. The circuit of claim 11 , further comprising said power transistor with the gate terminal and a source-drain path coupled to said output node.

13. The circuit of claim 11 , further comprising a resistor coupled between the reference node and a drive node of the power transistor across which the reference voltage is generated.

14. The circuit of claim 13 , further comprising:
a first current source configured to generate a first current for application to said reference node;
a second current source configured to generate a second current;
a switching circuit configured to selectively couple the second current to said reference node in response to a stress test enable signal;
wherein the reference voltage at the reference node has a lower value as a function of the first current when stress test is not enabled and has a higher value as a function of the first and second currents when stress test is enabled.

15. The circuit of claim 14 , wherein said generator circuit is configured to disconnect from the gate terminal of the power transistor when stress test is enabled.

16. The circuit of claim 11 , further comprising a resistor coupled between the output of the current mirroring circuit and the output node.

17. The circuit of claim 11 , wherein said first and second transistors apply a variable clamping voltage to the gate terminal of the power transistor in response to a stress test enable signal, said variable clamping voltage being lower when stress test is not enabled and higher when gate stress test is enabled.

18. A drive circuit for a power transistor having a gate terminal and an output terminal, comprising:
a generator circuit configured to apply a drive control signal the gate terminal of the power transistor in order to drive said output terminal;
a reference voltage generator configured to generate a reference voltage at a reference node having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use during stress testing;
circuitry coupled between the reference node and the gate terminal of the power transistor, said circuitry operable to function as a variable gate clamping circuit exhibiting:
a first clamping voltage applied to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal; and
a second, higher, clamping voltage applied to clamp the voltage at the gate of the power transistor when the generator circuit is disconnected from the gate of the power transistor during gate stress testing mode.

19. The drive circuit of claim 18 , wherein said circuitry comprises:
a first transistor having a gate terminal coupled to the gate terminal of the power transistor; and
a second transistor;
wherein source-drain paths of said first and second transistors are coupled in series between said reference node and the gate terminal of the power transistor.

20. The drive circuit of claim 19 , wherein said circuitry further comprises:
a third transistor coupled with the second transistor to form a current mirroring circuit; and
a fourth transistor having a source-drain path coupled between the gate terminal of the power transistor and the output terminal and a gate terminal coupled to an output of the current mirroring circuit.

21. The circuit of claim 18 , wherein said reference voltage generator comprises:
a first current source configured to generate a first current for application to said reference node;
a second current source configured to generate a second current;
a switching circuit configured to selectively couple the second current to said reference node in response to a stress test enable signal;
wherein the first voltage value is a lower value set as a function of the first current the generator circuit is appl

Assignees

• Stmicroelectronics Shenzhen R&D Co Ltd
• Stmicroelectronics Shenzhen R&D Co Ltd

Inventors

• Zeng Ni

Classifications

• G01R31/2621

  for testing field effect transistors, i.e. FET's · CPC title

• H03K17/08122

  in field-effect transistor switches · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K5/08 Primary

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• H03K3/011 Primary

  Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title