Integrated circuit package and method of forming the same

Patent metadata

Field	Value
Publication number	US-9455241-B2
Application number	US-201514754230-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Jan 26, 2009
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

First claim

What is claimed is:

1. A method of forming an integrated circuit package comprising:
forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from 45 degrees to 135 degrees;
forming an adhesive material on the first portion of the lead frame;
attaching a carrier to the lead frame with the adhesive material;
attaching an integrated circuit to the adhesive material;
forming an interconnect on the integrated circuit;
forming a protective material on the integrated circuit;
removing the carrier and the adhesive material;
removing a portion of the protective material to expose the interconnect and the second portion of the lead frame; and
removing the first portion of the lead frame.

2. The method of claim 1 , wherein the angle is in the range from 85 degrees to 95 degrees.

3. The method of claim 1 , wherein forming the protective layer comprises heating an epoxy material to a temperature in the range from 120° C. to 150° C. to harden the epoxy material.

4. The method of claim 3 , wherein removing the carrier and the adhesive material comprises heating the epoxy material to a temperature from 175° C. to 260° C. to thermally release the adhesive material and carrier.

5. The method of claim 1 , wherein removing the portion of the protective material comprises grinding an upper surface thereof.

6. The method of claim 1 , further comprising:
forming a conductive material on the protective layer;
forming a passivation layer on the conductive material; and
forming a solder ball on the passivation layer, wherein the solder ball is electrically coupled to the conductive material.

7. A method of making an integrated circuit package comprising:
forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from 45 degrees to 135 degrees;
adhering a double-sided thermal tape to a bottom surface of the first portion of the lead frame;
attaching a carrier to the lead frame with the double-sided thermal tape;
attaching an integrated circuit to the double-sided thermal tape adjacent to the first portion of the lead frame;
forming at least one pillar interconnect on the integrated circuit;
forming a compressive compound over the integrated circuit and the first and second portions of the lead frame;
hardening the compressive compound by heating the compressive compound to a temperature in the range from 120° C. to 150° C.;
removing a portion of the compressive compound to expose the at least one pillar interconnect and the second portion of the lead frame; and
removing the first portion of the lead frame.

8. The method of claim 7 , wherein the removing the portion of compressive compound comprises grinding an upper surface thereof.

9. The method of claim 8 , further comprising:
forming a conductive material on the compressive compound;
forming a first passivation layer on an upper surface of the conductive material;
forming a second passivation layer on a lower surface of the compressive compound; and
forming a solder ball on the first passivation layer, wherein the solder ball is electrically coupled to the conductive material.

10. The method of claim 7 , wherein the compressive compound comprises an epoxy material.

11. The method of claim 7 , further comprising attaching a component to the lower surface of the compressive compound.

12. A method of forming an integrated circuit package comprising:
forming a lead frame comprising a first portion and a second portion transverse to the first portion;
forming an adhesive material on the first portion of the lead frame;
attaching a carrier to the lead frame with the adhesive material;
attaching an integrated circuit to the adhesive material;
forming an interconnect on the integrated circuit;
forming a protective material on the integrated circuit;
removing the carrier and the adhesive material;
removing a portion of the protective material to expose the interconnect and the second portion of the lead frame; and
removing the first portion of the lead frame.

13. The method of claim 12 , wherein forming the protective material comprises heating an epoxy material to a temperature in the range from 120° C. to 150° C. to harden the epoxy material.

14. The method of claim 13 , wherein removing the carrier and the adhesive material comprises heating the epoxy material to a temperature from 175° C. to 260° C. to thermally release the adhesive material and carrier.

15. The method of claim 12 , wherein removing the portion of the protective material comprises grinding an upper surface thereof.

16. The method of claim 12 further comprising:
forming a conductive material on the protective material;
forming a passivation layer on the conductive material; and
forming a solder ball on the passivation layer, wherein the solder ball is electrically coupled to the conductive material.

Assignees

• St Microelectronics Pte Ltd

Inventors

• Jin Yonggang
• Kuwabara Kiyoshi
• Baraton Xavier

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title