EEPROM memory cell with low voltage read path and high voltage erase/write path

Patent metadata

Field	Value
Publication number	US-9455037-B2
Application number	US-201414209275-A
Country	US
Kind code	B2
Filing date	Mar 13, 2014
Priority date	Mar 15, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

First claim

The invention claimed is:

1. An electrically erasable programmable read only memory (EEPROM) cell, comprising:
a substrate including at least one active region;
a floating gate above the substrate;
a write/erase gate arranged above the floating gate and defining a write/erase path for performing write and erase operations of the cell; and
a read gate arranged above the substrate and laterally adjacent to the floating gate and the write/erase gate, the read gate defining a read path for performing read operations of the cell, wherein the read path is distinct from the write/erase path,
a floating gate oxide between the floating gate and the substrate; and
a read gate oxide between the read gate and the substrate;
wherein the read gate oxide is thinner than the floating gate oxide.

2. The EEPROM cell of claim 1 , wherein:
the write/erase gate and the floating gate form a stack and wherein the read gate has a vertical extension extending beyond the vertical extension of the stack.

3. The EEPROM cell of claim 2 , comprising:
a dielectric hard mask covering the write/erase gate wherein the read gate extends to a top surface of the dielectric hard mask.

4. The EEPROM cell of claim 1 , wherein:
the write/erase path defined by the write/erase gate is configured for high voltage write and erase operations; and
the read path defined by the read gate is configured for low voltage read operations.

5. The EEPROM cell of claim 1 , wherein:
an active region of the substrate is self-aligned with the read gate.

6. The EEPROM cell of claim 1 , wherein the read gate includes first and second portions formed on opposite sides of the floating gate, such that the floating gate is arranged between the first and second portions of the read gate.

7. The EEPROM cell of claim 1 , comprising first and second read gates that are independently controllable.

8. The EEPROM cell of claim 7 , wherein:
the first read gate is formed adjacent a first lateral side of the floating gate; and the second read gate is formed adjacent a second lateral side of the floating gate.

9. A method of operating an electrically erasable programmable read only memory (EEPROM) cell having a substrate including at least one doped well, a floating gate formed over the substrate, a low voltage read path defined by a read gate being arranged above the substrate and laterally adjacent to the floating gate and the write/erase gate, and a separate high voltage write/erase path defined by a write/erase gate distinct from the at least one read gate, wherein the write/erase gate is arranged above the floating gate, and the read gate is arranged above the substrate and laterally adjacent to the floating gate and the write/erase gate, and further comprising a floating gate oxide between the floating gate and the substrate, and a read gate oxide between the read gate and the substrate, wherein the read gate oxide is thinner than the floating gate oxide, the method comprising:
performing a write operation to charge the floating gate by creating a high voltage differential between the write/erase gate and the at least one doped well; and
performing a read operation to read the charge on the floating gate by creating a low voltage differential between the read gate and the at least one doped well.

10. The method of claim 9 , further comprising performing an erase operation to discharge the floating gate by creating a high voltage differential between the at least one doped well and the write/erase gate.

11. The method of claim 9 , wherein the EEPROM cell is an n-channel cell comprising at least one p-well, and the method comprises:
performing the read operation to read the charge on the floating gate by applying a low read voltage bias to the write/erase gate while grounding the at least one p-well;
performing the write operation to charge the floating gate by applying a high write voltage bias to the write/erase gate while grounding the at least one p-well; and
performing an erase operation to discharge the floating gate by applying a high erase voltage bias to the at least one p-well while grounding the write/erase gate, wherein the high erase voltage bias may be the same or different voltage than the high write voltage bias.

12. The method of claim 9 , wherein the EEPROM cell is a p-channel cell comprising at least one n-well, and the method comprises:
performing the read operation to read the charge on the floating gate by applying a low read voltage bias to the at least one n-well while grounding the write/erase gate;
performing the write operation to charge the floating gate by applying a high write voltage bias to the at least one n-well while grounding the write/erase gate; and
performing an erase operation to discharge the floating gate by applying a high erase voltage bias to the write/erase gate while grounding the at least one n-well, wherein the high erase voltage bias may be the same or different voltage than the high write voltage bias.

13. The method of claim 9 , wherein the EEPROM cell includes first and second read gates, and wherein the method comprises independently biasing the first and second read gates.

14. The method of claim 13 , wherein the first and second read gates comprise poly spacers located on opposite lateral sides of the floating gate.

15. A memory cell array, comprising:
a plurality electrically erasable programmable read only memory (EEPROM) cells arranged in an array, each EEPROM cell comprising:
a substrate including at least one active region;
a floating gate arranged over the substrate;
a write/erase gate arranged above the floating gate and defining a write/erase path for performing write and erase operations of the cell; and
a read gate arranged above the substrate and laterally adjacent to the floating gate and the write/erase gate, the read gate defining a read path for performing read operations of the cell, wherein the read path is distinct from the write/erase path,
a floating gate oxide between the floating gate and the substrate; and
a read gate oxide between the read gate and the substrate;
wherein the read gate oxide is thinner than the floating gate oxide.

16. The memory cell array of claim 15 , wherein:
the array of EEPROM cells comprises a plurality of cell rows; and at least two cell rows share a common source line.

17. The memory cell array of claim 15 , wherein for each EEPROM cell: the write/erase gate and the floating gate form a stack and wherein the read gate has a vertical extension extending beyond the vertical extension of the stack.

18. The memory cell array of claim 15 , wherein each EEPROM cell comprises: a dielectric hard mask covering the write/erase gate wherein the read gate extends to a top surface of the dielectric hard mask.

19. The memory cell array of claim 15 , wherein for each EEPROM cell:
the write/erase path defined by the write/erase gate is configured for high voltage write and erase operations; and
the read path defined by the read gate is configured for low voltage read operations.

20. The memory cell array of claim 15 , each EEPROM cell includes first and second read gates that are independently controllable.

21. The method of claim 9 , wherein:
the write/erase gate and the floating gate form a stack and wherein the read gate has a vertical extension extending beyond the vertical extension of the stack.

22. The method of claim 21 , comprising:
a dielectric hard mask covering the write/erase gate wherein the read

Assignees

• Microchip Tech Inc

Inventors

• Hewitt Kent
• Wong Jack
• Chen Bomy
• Daryanani Sonu
• Shields Jeffrey A
• Alvarez Daniel
• Hymas Mel

Classifications

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• G11C16/0416 Primary

  comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM · CPC title

• H01L29/7881

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic