Computing platform performance management with RAS services

Patent metadata

Field	Value
Publication number	US-9454380-B2
Application number	US-201213977593-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 22, 2011
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS RAS services for one or more hardware components, regardless of a particular platform hardware configuration, as long as the platform hardware and OS are in conformance with the PPM interface.

First claim

What is claimed is:

1. A computing platform, comprising:
a non-volatile memory having a firmware boot program; and
a processor to execute the firmware boot program when the processor is reset, the firmware boot program including instructions is to create Performance and Power Management (PPM) interface data structures including a Reliability Accessibility Serviceability (RAS) table structure, wherein the RAS table structure comprises a table for a RAS table format which is compatible with an Advanced Configuration and Power Interface (ACPI) implementation.

2. The computing platform of claim 1 , in which the RAS table structure comprises a table for a RAS features (RASF) platform communication channel (PCC) shared memory region.

3. The computing platform of claim 2 , in which the RAS table structure comprises a table for PCC command codes used by a RASF PCC structure.

4. The computing platform of claim 1 , in which the RAS table structure comprises a table for identifying RAS capabilities bitmap.

5. The computing platform of claim 1 , in which the RAS table structure comprises a table for indicating parameter block structure for a PATROL SCRUB task.

6. The computing platform of claim 1 , in which the RAS table structure comprises a table for indicating a parameter block structure for one or more commands to indicate, to an Operating System (OS), reliability information for memory.

7. The computing platform of claim 6 , in which the reliability information pertains to available reliable flash memory write cycles.

8. The computing platform of claim 1 , in which the boot program comprises an Extensible Firmware Interface (EFI) program.

9. A computing platform, comprising:
a first memory storage device having instructions for an operating system (OS) including OS Performance and Power Management (PPM) components for a PPM interface; and
a second memory storage device, coupled to the first memory storage device via at least one integrated circuit, the second memory storage device having instructions for a firmware boot program including firmware PPM components for a PPM interface, the OS and firmware PPM instructions, when executed, are to establish a PPM interface between the OS and platform hardware, wherein the PPM interface includes a Reliability Accessibility Serviceability (RAS) data structure, to provide to the OS, RAS services.

10. The computing platform of claim 9 , in which the OS is to identify available RAS services from the RAS data structure.

11. The computing platform of claim 10 , in which the OS is to issue a command through a platform communications channel to receive an RAS service.

12. The computing platform of claim 9 , in which the RAS data structure is to be updated at least by a firmware routine initiated from a system interrupt.

13. The computing platform of claim 12 , comprising at least one RAS provider to provide data to update the RAS data structure.

14. The computing platform of claim 12 , in which the firmware routine is to be called by an interrupt routine.

15. The computing platform of claim 9 , in which updatable parts of the RAS structure are to exist in memory that is reserved by the firmware boot program.

16. An apparatus, comprising:
a computer platform having firmware including ACPI components to build a RAS features (RASF) table structure, wherein the RASF table structure comprises a platform RAS capabilities bitmap structure; and wherein the RASF table structure comprises a parameter block structure for memory scrub services.

Assignees

• Intel Corp

Inventors

• Kumar Mohan
• Jayakumar Sarathy
• Vargas Jose Andy

Classifications

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title

• G06F9/384

  Register renaming · CPC title