Packaging device and method of making the same

Patent metadata

Field	Value
Publication number	US-9449933-B2
Application number	US-201213434256-A
Country	US
Kind code	B2
Filing date	Mar 29, 2012
Priority date	Mar 29, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface of the metal trace.

First claim

What is claimed is:

1. A device comprising:
a first package component;
a metal trace on a surface of the first package component, wherein the metal trace has a lengthwise direction, and wherein the metal trace comprises an undercut along the lengthwise direction;
a molding material that fills the undercut along the lengthwise direction of the metal trace and slopes downwardly away from a side of the metal trace along the lengthwise direction, a top portion of the side of the metal trace being free of the molding material and an entirety of the molding material being below a top surface of the metal trace; and
a solder region contacting the top surface and the top portion of the side of the metal trace above the molding material.

2. The device of claim 1 , further comprising:
a metal pillar arranged between the solder region and a metal pad on a surface of a second package component;
an under-bump metallurgy having a non-planar topology, which is arranged between the metal pillar and the metal pad; and
wherein the second package component is disposed over the first package component and the solder region contacts the metal pillar.

3. The device of claim 1 , wherein the metal trace comprises copper, tungsten, nickel, palladium, gold, or alloys thereof.

4. The device of claim 2 , wherein the second packaging component comprises a substrate, and wherein an interconnect structure, which includes metal lines and vias formed therein, is formed over the substrate.

5. The device of claim 4 , wherein the interconnect structure comprises an inter-layer dielectric layer.

6. The device of claim 2 , wherein the metal pillar comprises a copper pillar or a copper-containing bump.

7. The device of claim 1 , wherein the molding material comprises a curable organic composition comprising curable epoxies, curable cyanate esters, or combinations thereof.

8. The device of claim 1 , wherein the molding material comprises a curable silicone composition comprising a condensation reaction curable silicone composition, an addition reaction curable silicone composition, an ultraviolet radiation initiated curable silicone composition, or a free radical initiated curable silicone composition.

9. A method of making a semiconductor packaging device comprising:
providing a packaging component containing metal traces that have undercuts;
applying a molding material over the packaging component so that the molding material fills the undercuts;
plasma treating a surface of the packaging component to remove portions of the molding material such that the molding material slopes downwardly away from sides of the metal traces above the undercuts, top portions of the sides of the metal traces above the undercuts being free of the molding material, and an entirety of the molding material being below top surfaces of the metal traces; and
forming a solder region contacting the top surfaces and top portions of the sides of the metal traces above the molding material.

10. The method of claim 9 , wherein the molding material comprises a curable organic composition, a curable silicone-organic copolymer composition, or a curable silicone composition.

11. The method of claim 9 , further comprising curing the molding material at a temperature ranging from 80° C. to 240° C. for a period ranging from 30 seconds to 120 seconds.

12. A package comprising:
a first package component comprising:
a metal trace on a surface of the first package component, wherein the metal trace has a lengthwise direction, and wherein the metal trace comprises an undercut along the lengthwise direction; and
a molding material that fills the undercut along the lengthwise direction of the metal trace and slopes downwardly away from a first side of the metal trace along the lengthwise direction, an entirety of the molding material being below a top surface of the metal trace;

a second package component disposed over the first package component, the second package component comprising:
a metal pillar; and
a solder region bonding the metal pillar to the metal trace, wherein the solder region contacts the top surface of the metal trace and opposing sides of the metal trace adjacent to the top surface and above the molding material, the opposing sides of the metal trace including the first side.

13. The device of claim 1 , wherein the metal trace extends beyond the solder region in the lengthwise direction.

14. The device of claim 1 , wherein the solder region contacts the metal trace along a planar interface that extends between outer edges of the solder region.

15. The device of claim 2 , further comprising:
a passivation layer arranged onto the surface of the second package component and extending over the metal pad to a position abutting sidewalls of the under-bump metallurgy.

16. The method of claim 9 , wherein the metal traces extend beyond opposing edges of the solder region.

17. The method of claim 9 , wherein the solder region contacts the metal traces along a planar interface that extends between outer edges of the solder region.

18. The package of claim 12 , wherein the metal trace extends beyond the solder region in the lengthwise direction.

19. The package of claim 12 , wherein the solder region contacts the metal trace along a planar interface that extends between outer edges of the solder region.

Assignees

• Huang Chang-Chia
• Lin Tsung-Shu
• Cheng Ming-Da
• Lu Wen-Hsiung
• Su Bor-Rung
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Chang-Chia
• Lin Tsung-Shu
• Cheng Ming-Da
• Lu Wen-Hsiung
• Su Bor-Rung

Classifications

• H10W70/6525

  for securing the interconnections to the substrate, e.g. to prevent peeling · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title