Substrate and assembly thereof with dielectric removal for increased post height

Patent metadata

Field	Value
Publication number	US-9318460-B2
Application number	US-201414513563-A
Country	US
Kind code	B2
Filing date	Oct 14, 2014
Priority date	Jun 8, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

First claim

The invention claimed is:

1. An interconnection substrate, comprising:
a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions;
electrically conductive projections having bonding surfaces for bonding to electrically conductive contacts of at least one component external to the substrate, the conductive projections extending from the conductive elements above the at least one wiring layer, the conductive projections having concave edge surfaces extending inwardly and downwardly from the bonding surfaces towards the conductive elements; and
a solder resist layer extending along exposed surfaces of the conductive elements and extending along the concave edge surfaces so as to prevent a bonding metal from wicking away from the bonding surfaces and inwardly and downwardly along the concave edge surfaces, the solder resist layer between the conductive projections being recessed below a height of the bonding surfaces.

2. The interconnection substrate of claim 1 , wherein the bonding surfaces meet the concave edge surfaces at a boundary, and wherein the bonding surfaces and the concave edge surfaces together form a continuous edge surface that changes direction abruptly at the boundary.

3. The interconnection element of claim 2 , wherein the solder resist layer is disposed at the boundary.

4. The interconnection substrate of claim 2 , wherein respective portions of the solder resist layer extend along the concave edge surfaces to top edges near the boundary.

5. The interconnection substrate of claim 4 , wherein portions of the solder resist layer extending along the concave edge surfaces of the conductive projections define concave edge surfaces of the solder resist layer portions.

6. The interconnection substrate of claim 1 , wherein the bonding surfaces are convex.

7. The interconnection substrate of claim 1 , wherein upper portions of the concave edge surfaces extend outwardly and at least partially face toward the wiring layer.

8. The interconnection substrate of claim 1 , further including solder balls extending along at least the bonding surfaces of the conductive projections, and wherein the solder balls define lower edges along the conductive projections and spaced apart from the recessed portions by portions of the solder resist layer.

9. A microelectronic assembly, comprising:
the interconnection substrate of claim 8 ; and
a microelectronic element having a front face with contacts exposed thereon and a back face spaced apart from the front face,
wherein the first face of the microelectronic element faces the solder resist layer and wherein the solder balls are joined to respective ones of the contacts of the microelectronic element.

10. The microelectronic assembly of claim 9 , wherein the front face of the microelectronic element is spaced apart from the recessed portions of the solder resist layer at a first distance, and wherein the solder balls define portions of a sphere having diameters that are less than the first distance.

11. The microelectronic assembly of claim 10 , wherein an encapsulant extends between the solder resist layer and the front face of the microelectronic element.

12. A method for making a microelectronic substrate, comprising the steps of:
forming a solder resist layer on an in-process unit including a wiring layer having a plurality of conductive elements extending in first and second lateral directions and a plurality of conductive projections extending away from the elements above the wiring layer, the electrically conductive projections having bonding surfaces for bonding to electrically conductive contacts of at least one component external to the substrate, the conductive projections having concave edge surfaces extending inwardly and downwardly from the bonding surfaces towards the conductive elements, the solder resist layer extending along exposed surfaces of the conductive elements and extending along the concave edge surfaces so as to prevent a bonding metal from wicking away from the bonding surfaces and inwardly and downwardly along the concave edge surface; and
removing portions of the solder resist layer to form recessed portions between the projections.

13. The method of claim 12 , wherein the step of removing portions of the solder resist layer is carried out such that portions of the solder resist layer remain extending along the concave edge surfaces to a boundary formed between the edge surface and the bonding surface.

14. The method of claim 12 , wherein the bonding surfaces are convex.

15. The method of claim 12 , wherein the step of removing portions is carried out such that the solder resist layer is positioned at least partially below the bonding surfaces.

16. The method of claim 12 , wherein the step of removing portions of the solder resist layer is carried out by a wet-blasting process.

17. The method of claim 16 , wherein the wet-blasting process deforms the bonding surfaces the projections to define convex surfaces thereon.

18. The method of claim 16 , wherein the wet-blasting process further deforms the bonding surfaces such that a periphery of the bonding surface widens along at least a portion thereof.

Assignees

• Tessera Inc

Inventors

• Sakuma Kazuo
• Damberg Philip
• Haba Belgacem

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title