Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby

Patent metadata

Field	Value
Publication number	US-9449870-B2
Application number	US-201514943532-A
Country	US
Kind code	B2
Filing date	Nov 17, 2015
Priority date	Aug 22, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
alternatingly stacking a plurality of first layers and second layers to form a stack, the stack having a first region and a second region, and the stack having a vertical pitch of a distance between a top surface of one first layer and a top surface of another first layer adjacent to the one first layer;
first patterning the stack, the first patterning comprising multilayer etching at least one from among the first and the second regions to a first depth that is at least twice the vertical pitch; and
second patterning the stack, the second patterning comprising single layer etching at least another from among the first and the second regions to a second depth that is approximately equal to the vertical pitch,
wherein a shape of a first profile of the first region is offset from a shape of a second profile of the second region, the offset being an amount equal to at least the vertical pitch.

2. The method of claim 1 , wherein the shape of the first profile and the shape of the second profile are same.

3. The method of claim 2 , wherein in the first patterning, the multilayer etching is performed once or repeatedly performed on multiple areas of the first and the second regions with a mask or masks of different shapes so the first and the second profile shapes have stepped shapes.

4. The method of claim 3 , wherein the second patterning comprises single layer etching the second region.

5. The method of claim 4 , wherein the one first layer of the plurality of first layers includes a connection portion and an aligned portion, the connection portion being disposed at the first region and connected to a conductive plug and the aligned portion being disposed at the second region and aligned with a connection portion of another first layer disposed on the one first layer.

6. The method of claim 5 , wherein the connection portion of the other first layer is disposed above the aligned portion of the one first layer and the aligned portion of the other first layer is not aligned over the connection portion of the one first layer.

7. The method of claim 6 , wherein the first patterning is performed before the second patterning.

8. The method of claim 6 , wherein the second patterning is performed before the first patterning.

9. The method of claim 1 , wherein the multilayer etching the first and the second regions is a first multilayer etching based on a first mask, and the first patterning further comprising a second multilayer etching the first and the second regions based on a second mask,
and wherein the second mask is smaller than the first mask.

10. The method of claim 9 , wherein the first region and the second region are at opposite ends of the stack.

11. The method of claim 9 , wherein the stack includes one end and another end that are disposed at opposite sides of the stack, and wherein the first and the second regions are disposed at the one end of the stack.

12. The method of claim 1 , wherein in the first patterning, the multilayer etching is performed once on the second region with a mask.

13. The method of claim 12 , wherein in the second patterning, the single layer etching is performed once or repeatedly performed on multiple areas of the first and the second regions with a mask or masks of different shapes so the first and the second profile shapes have stepped shapes.

14. The method of claim 13 , wherein the one first layer of the plurality of first layers includes a connection portion and an aligned portion, the connection portion being disposed at the first region, which is connected to a conductive plug and the aligned portion being disposed at the second region, which is aligned with a connection portion of another first layer disposed on the one first layer.

15. The method of claim 14 , wherein the connection portion of the other first layer is disposed above the aligned portion of the one first layer and the aligned portion of the other first layer is not aligned over the connection portion of the one first layer.

16. The method of claim 15 , wherein the first patterning is performed before the second patterning.

17. The method of claim 15 , wherein the second patterning is performed before the first patterning.

18. The method of claim 12 , wherein the single layer etching the first and the second regions is a first single layer etching based on a first mask, and the second patterning further comprising a second single layer etching the first and the second regions based on a second mask,
and wherein the second mask is smaller than the first mask.

19. The method of claim 18 , wherein the first and the second regions are at opposite ends of the stack.

20. The method of claim 12 , wherein the multilayer etching is a first multilayer etching, the method further comprising a third patterning, the third pattering comprising a second multilayer etching the first and the second regions, wherein the second multilayer etching etches to a second depth that is greater than the first distance.

21. The method of claim 20 , wherein the first, the second, and the third patterning overlap in the vertical direction.

22. A method of manufacturing a semiconductor device, the method comprising:
alternatingly stacking a plurality of sacrificial layers and insulating layers to form a stack, the stack having a first region at one side of the stack and a second region at another side of the stack;
first patterning the plurality of sacrificial and insulating layers, the first patterning comprising repeatedly etching the first region to form a first stepped profile at the first region; and
second patterning the plurality of sacrificial and insulating layers, the second patterning, comprising repeatedly etching the second region to form a second stepped profile that is lower than the first stepped profile at the first region;
wherein the first and the second patterning form a dummy pattern between the first region and the second region.

23. The method of claim 22 , wherein a top of the dummy pattern and a top of the first stepped profile region are at a same level.

24. A method of manufacturing a semiconductor device, the method comprising:
alternatingly stacking a plurality of horizontal layers and insulating layers to form a stack, the stack having a first region and a second region disposed at one end of the stack, and having a vertical pitch, the vertical pitch being a distance between top surfaces of one horizontal layer and an adjacent horizontal layer;
first patterning the plurality of horizontal and insulating layers, the first patterning comprising multilayer etching at least one from among the first and the second regions to a first depth that is at least twice the vertical pitch; and
second patterning the plurality of horizontal and insulating layers, the second patterning comprising single layer etching at least one from among the first and the second regions to a second depth that is approximately equal to the vertical pitch,
wherein a first profile of an etched portion of the first region of the plurality of horizontal and insulating layers is offset from a second profile of an etched portion of the second region of the plurality of horizontal and insulating layers, the offset being an amount equal to the vertical pitch and
wherein the first profile overlaps the second profile in a horizontal direction.

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Assignees

• Eun Dongseog
• Lee Young-Ho
• Lee Joonhee
• Lee Seok-Won
• Shin Yoocheol
• Samsung Electronics Co Ltd

Inventors

• Eun Dongseog
• Lee Young-Ho
• Lee Joonhee
• Lee Seok-Won
• Shin Yoocheol

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title