Reducing Retention Loss in Analog Floating Gate Memory
US-2015364480-A1 · Dec 17, 2015 · US
US9449851B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9449851-B2 |
| Application number | US-201514833407-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 24, 2015 |
| Priority date | Aug 29, 2014 |
| Publication date | Sep 20, 2016 |
| Grant date | Sep 20, 2016 |
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This disclosure provides systems, methods, and apparatus related to locally doping two-dimensional (2D) materials. In one aspect, an assembly including a substrate, a first insulator disposed on the substrate, a second insulator disposed on the first insulator, and a 2D material disposed on the second insulator is formed. A first voltage is applied between the 2D material and the substrate. With the first voltage applied between the 2D material and the substrate, a second voltage is applied between the 2D material and a probe positioned proximate the 2D material. The second voltage between the 2D material and the probe is removed. The first voltage between the 2D material and the substrate is removed. A portion of the 2D material proximate the probe when the second voltage was applied has a different electron density compared to a remainder of the 2D material.
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What is claimed is: 1. A method comprising: (a) forming an assembly including a substrate, a first insulator disposed on the substrate, a second insulator disposed on the first insulator, and a two-dimensional (2D) material disposed on the second insulator; (b) applying a first voltage between the 2D material and the substrate; (c) with the first voltage applied between the 2D material and the substrate, applying a second voltage between the 2D material and a probe positioned proximate the 2D material; (d) removing the second voltage between the 2D material and the probe; and (e) removing the first voltage between the 2D material and the substrate, a portion of the 2D material proximate the probe in operation (c) having a different electron density compared to a remainder of the 2D material. 2. The method of claim 1 , wherein the 2D material comprise about 10 monolayers of material or less. 3. The method of claim 1 , wherein the 2D material comprises graphene. 4. The method of claim 1 , wherein the 2D material is selected from a group consisting of molybdenum disulfide, molybdenum diselenide, tungsten disulfide, and tungsten diselenide. 5. The method of claim 1 , wherein the probe is positioned about 10 nanometers or less from the 2D material in operation (c). 6. The method of claim 1 , wherein the second voltage applied between the 2D material and the probe in operation (c) is about −100 volts to +100 volts. 7. The method of claim 1 , wherein the second voltage applied between the 2D material and the probe in operation (c) is about +5 volts or higher. 8. The method of claim 1 , wherein the second voltage applied between the 2D material and the probe in operation (c) is about −3 volts or lower. 9. The method of claim 1 , wherein the second voltage applied between the 2D material and the probe in operation (c) is applied for about 0.1 seconds to 5 minutes. 10. The method of claim 1 , wherein the first voltage applied between the 2D material and the substrate in operation (b) is about −150 volts to about +150 volts. 11. The method of claim 1 , wherein the first insulator comprises a material selected from a group consisting of silicon oxide, hafnium oxide, and aluminum oxide, wherein the second insulator comprises a material selected from a group consisting of boron nitride and a silicate mineral, and wherein the substrate comprises a material selected from a group consisting of a doped semiconductor, a layered semimetal, and a metal. 12. The method of claim 1 , wherein the first insulator has a greater band gap than the second insulator. 13. The method of claim 1 , wherein the probe comprises a conductive material. 14. The method of claim 1 , wherein the probe comprises a metal wire or a carbon nanotube. 15. The method of claim 1 , wherein the probe comprises a conductive substrate and a pattern disposed on a surface the conductive substrate comprising a conductive material. 16. The method of claim 1 , wherein the first insulator is about 10 nanometers to 500 nanometers thick. 17. The method of claim 1 , wherein the second insulator is about 5 nanometers to 300 nanometers thick. 18. The method of claim 1 , wherein the substrate has a thickness of about 50 nanometers or greater.
being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title
Carbon, e.g. diamond-like carbon · CPC title
consisting of two layers · CPC title
being insulating materials · CPC title
Silicon, silicon germanium or germanium · CPC title
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