Forward error correction with configurable latency

Patent metadata

Field	Value
Publication number	US-9448885-B2
Application number	US-201514728588-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Nov 26, 2010
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.

First claim

We claim:

1. A method, comprising:
storing data in locations of a configurable buffer;
performing forward error correction on the data as it is transmitted through configurable buffer; and
adjusting the locations based on a comparison between a target error rate and a computed error rate, wherein the computed error rate is computed based on the forward error correction of the stored data.

2. The method of claim 1 , wherein the adjusting the locations comprises reducing a number of the locations if the computed error rate is less than or equal to the target error rate.

3. The method of claim 1 , wherein the adjusting the locations comprises increasing a number of the locations if the computed error rate is greater than the target error rate.

4. The method of claim 1 , wherein the locations are adjusted until the computed error rate is substantially equal to or less than the target error rate.

5. The method of claim 1 , wherein the locations are adjusted until a minimum number of locations is reached that results in the computed error rate being substantially equal to or less than the target error rate.

6. The method of claim 1 , wherein a number of the locations of the configurable buffer corresponds to a size of the configurable buffer.

7. The method of claim 1 , wherein the forward error correction code is a Bose Ray-Chaudhuri (BCH) code.

8. An apparatus, comprising:
a configurable buffer, wherein locations of the configurable buffer store data;
a forward error correction block configured to perform forward error correction on the data as the data is transmitted through the configurable buffer; and
logic circuitry configured to adjust the locations based on a comparison between a target error rate and a computed error rate, wherein the computed error rate is computed based on the forward error correction of the stored data.

9. The apparatus of claim 8 , wherein the logic circuitry adjusts the locations by reducing a number of the locations if the computed error rate is less than or equal to the target error rate.

10. The apparatus of claim 8 wherein the logic circuitry adjusts the locations by increasing a number of the locations if the computed error rate is greater than the target error rate.

11. The apparatus of claim 8 , wherein the locations are adjusted until the computed error rate is substantially equal to or less than the target error rate.

12. The apparatus of claim 8 , wherein the locations are adjusted until a minimum number of locations is reached that results in the computed error rate being substantially equal to or less than the target error rate.

13. The apparatus of claim 8 , wherein a number of the locations of the configurable buffer corresponds to a size of the configurable buffer.

14. The apparatus of claim 8 , wherein the forward error correction code is a Bose Ray-Chaudhuri (BCH) code.

15. An apparatus for forward error correction, the apparatus comprising:
a configurable buffer configured to store data;
a forward error correction block configured to perform forward error correction on the data as the data is transmitted through the configurable buffer; and
logic circuitry configured to adjust a size of the configurable buffer based on a comparison between a target error rate and a computed error rate, wherein the computed error rate is computed based on the forward error correction of the stored data.

16. The apparatus of claim 15 , wherein the logic circuitry is configured to adjust the size by reducing the size if the computed error rate is less than or equal to the target error rate.

17. The apparatus of claim 15 , wherein the logic circuitry is configured to adjust the size by increasing the size if the computed error rate is greater than the target error rate.

18. The apparatus of claim 15 , wherein the size is adjusted until a minimum size is reached that results in the computed error rate being substantially equal to or less than the target, error rate.

19. The apparatus of claim 15 , wherein the size of the configurable buffer corresponds to a number of locations of the configurable buffer that store the data.

20. The apparatus of claim 15 , wherein the forward error correction code is a Bose Ray-Chaudhuri (BCH) code.

Assignees

• Altera Canada Co
• Altera Corp

Inventors

• Haas Wally
• Rumbolt Chuck

Classifications

• H03M13/152 Primary

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/102

  Error in check bits · CPC title

• H03M13/3738

  with judging correct decoding · CPC title