Low drift voltage reference

Patent metadata

Field	Value
Publication number	US-9448579-B2
Application number	US-201314136774-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

Circuits and method for providing voltage reference circuits that include low drift over time and lower operating voltages are provided. Generally, it is desirable that a reference circuit provide an accurate and precise reference over time. The voltage reference circuits described can provide for good long term stability, operation at lower voltages than prior designs, consistent output voltage with reduced variability due to process changes and mismatches, low noise in the reference voltage, and other advantages.

First claim

What is claimed is:

1. A voltage reference circuit comprising:
a zener diode, including an anode, a cathode, and a positive temperature coefficient for a voltage generated between the anode and the cathode; and a temperature compensation circuit, connected to the cathode of the zener diode, configured to provide a temperature stable output voltage reference by subtracting from the voltage at the cathode of the zener diode, a series of base-emitter voltage differences respectively provided by bipolar transistors having different emitter current densities, wherein the temperature compensation circuit includes a series of base-emitter voltage difference circuits to generate the series of base-emitter voltage differences, wherein a base emitter voltage difference circuit is arranged in a cell, the cell comprising: a plurality of bipolar transistors arranged in first, second and third arms of the cell and configured to generate a proportional to absolute temperature voltage at an output of the cell that is dependent on individual ones of the plurality of bipolar transistors, and wherein each of the first arm, second arm and third arms are coupled to a single bias current such that the bias current is divided into each of the arms and each of the arms compensates for base current variations in the other of the arms.

2. The voltage reference circuit of claim 1 , wherein the temperature compensation circuit includes a series of base-emitter voltage difference circuits to generate the series of base-emitter voltage differences, wherein the series of base-emitter voltage difference circuits include a first negative base-emitter voltage differential, ΔVbe, block and a second negative base-emitter voltage differential, ΔVbe, block, the first block and second block being cascaded relative to one another.

3. The voltage reference circuit of claim 1 wherein the temperature compensation circuit includes a series of base-emitter voltage difference circuits to generate the series of base-emitter voltage differences, wherein a base-emitter voltage difference circuit includes a first bipolar transistor having a first emitter area and a second bipolar transistor having a second different emitter area, and wherein the voltage reference circuit further includes a MOS device coupled to each of the first bipolar transistor and the second bipolar transistor such that a base-emitter voltage difference between each of the first bipolar transistor and second bipolar transistor is reflected across the MOS device source and drain.

4. The voltage reference circuit of claim 3 further comprising a third bipolar transistor coupled to each of a base and a collector of the first bipolar transistor to minimize base current impact.

5. The voltage reference circuit of claim 1 , wherein the proportional to absolute temperature voltage provided at the output of the cell is related to a base-emitter voltage difference, ΔVbe, generated from an emitter ratio of a first set of bipolar transistors operating at a first collector current density and a second set of bipolar transistors operating at a second, lower, collector current density, the cell being coupled to the zener diode so as to provide the ΔVbe as a negative ΔVbe contribution to balance positive temperature coefficient response characteristics of the zener diode.

6. The voltage reference circuit of claim 5 further comprising a MOS device and wherein the base-emitter voltage difference generated from the emitter area ratio is reflected across the MOS device source and drain to the output of the cell.

7. The voltage reference circuit of claim 1 , wherein each arm comprises at least one transistor provided in a PNP configuration, the cell being configured such that emitters of individual PNP transistors of each of the first, second and third arms are coupled to a common node that is biased by the same bias current.

8. The voltage reference circuit of claim 7 wherein a first arm of the cell comprises a PNP transistor having a unity emitter size and a second arm of the circuit comprises a PNP transistor having a multiple, n, emitter size, the circuit being configured to generate a voltage at the output of the cell that is first order independent of the bias current and proportional to the multiple n.

9. The voltage reference circuit of claim 7 comprising a plurality of bipolar transistors configured in an NPN configuration and wherein each of a first arm and a second arm of the cell comprises at least one NPN configured transistor and at least one PNP configured transistor, the first arm operating at a first collector current density and the second arm operating at a second, lower, collector current density, the circuit being configured to generate a base emitter voltage difference at the output of the cell.

10. The voltage reference circuit of claim 9 wherein the NPN configured transistors have a different emitter area than the PNP configured transistors.

11. The voltage reference circuit of claim 1 , wherein the bias current is provided by a current source coupled to a supply voltage of the circuit.

12. The voltage reference circuit of claim 1 , wherein individual transistors of the third arm are provided in a diode connected configuration.

13. The voltage reference circuit of claim 1 further comprising a trimming node whereby a trimming current can be introduced into the circuit to vary the temperature coefficient characteristics of the circuit.

14. The voltage reference circuit of claim 13 wherein the trimming current is either added into the circuit or subtracted out of the circuit to vary the temperature coefficient characteristics of the circuit.

15. The voltage reference circuit of claim 14 wherein the trimming current is coupled to the circuit elements configured to generate a negative base-emitter voltage differential, ΔVbe, component.

16. The voltage reference circuit of claim 1 , wherein the base-emitter voltage difference circuits are resistor-less.

17. A voltage reference circuit comprising:
a first set of circuit elements comprising a zener diode having a positive temperature coefficient for a voltage generated between an anode and a cathode of the zener diode;
a second set of circuit elements comprising a series of base-emitter voltage difference circuits that include ratiometrically scaled pairs of bipolar transistors configured to generate a-proportional to absolute temperate (PTAT) voltage, wherein a ratiometrically scaled pair of bipolar transistors includes a first bipolar transistor having a first emitter area and a second bipolar transistor having a second different emitter area scaled to the first emitter area; and
the circuit coupling each of the first and second set of circuit elements to subtract the PTAT voltage from a voltage at the cathode of the zener diode to generate a temperature stable voltage reference at an output of the circuit, wherein the second set of circuit elements are arranged in a cell, the cell comprising: a plurality of bipolar transistors arranged in first, second and third arms of the cell and configured to generate a proportional to absolute temperature voltage at an output of the cell that is dependent on individual ones of the plurality of bipolar transistors, and wherein each of the first arm, second arm and third arms are coupled to a single bias current such that the bias current is divided into each of the arms and each of the arms compensates for base current variations in the other of the arms.

18. The voltage reference circuit of claim 17 wherein the proportional to absolute temperature voltage pr

Assignees

• Analog Devices Global

Inventors

• Marinca Stefan

Classifications

• G05F3/185 Primary

  and field-effect transistors · CPC title