Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement

Patent metadata

Field	Value
Publication number	US-9448283-B2
Application number	US-201214421889-A
Country	US
Kind code	B2
Filing date	Aug 22, 2012
Priority date	Aug 22, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.

First claim

The invention claimed is:

1. A circuit arrangement for Logic Built-In Self-Test (LBIST) of a semiconductor device, the circuit arrangement comprising:
a clock source configured to generate a system clock having a system clock pulse duration and a system clock period;
a first clock division circuitry configured to derive a first punched-out clock from the system clock by periodically suppressing one or more successive clock pulses of the system clock to obtain the first punched-out clock having a pulse duration corresponding to the system clock pulse duration and a cycle time corresponding to a plurality of system clock periods;
a plurality of scan chains operable at the first punched-out clock, each scan chain having an associated output circuitry responsive to a leading edge of the first punched-out clock;
a second clock division circuitry configured to derive a second punched-out clock from the system clock by periodically suppressing one or more successive clock pulses of the system clock to obtain the second punched-out clock with a pulse duration corresponding to the system clock pulse duration and a cycle time corresponding to the cycle time of the first punched-out clock, the second punched-out clock having a delay of one or more system clock periods relative to the first punched-out clock;
a signature generation circuitry comprising a compacting logic, a sequential retiming element and a Multi-Input Signature Register;
the Multi-Input Signature Register being operable at the second punched-out clock, the Multi-Input Signature Register having an input circuitry responsive to a leading edge of the second punched-out clock;
the compacting logic having a plurality of compactor inputs connected to the output circuitries of the plurality of scan chains and a compactor output, and configured to compact signals provided to its inputs into a compacted output on its output;
the sequential retiming element being connected with a data input to the output of the compacting logic and connected with a data output to the input circuitry of the Multi-Input Signature Register;
the sequential retiming element being operable at the second punched-out clock, the data input of the sequential retiming element being responsive to a trailing edge of the second punched-out clock.

2. A circuit arrangement according to claim 1 , the first clock division circuitry comprising a first clock control element configured to receive the system clock and a first enable signal, and to derive the first punched-out clock from the system clock by gating the system clock with the first enable signal.

3. A circuit arrangement according to claim 2 , the second clock division circuitry comprising a second clock control element configured to receive the system clock and a second enable signal, and to derive the second punched-out clock from the system clock by gating the system clock with the second enable signal.

4. A circuit arrangement according to claim 3 , the second clock division circuitry comprising a delay element configured to receive the system clock and the first enable signal and to establish the second enable signal from delaying the first enable signal with one or more successive clock cycles of the system clock.

5. A circuit arrangement according to claim 1 , further comprising:
a further clock division circuitry configured to derive a further punched-out clock from the system clock by periodically suppressing one or more successive clock pulses of the system clock corresponding to the suppressed clock pulses in deriving the first punched-out clock; and
a further plurality of scan chains, each scan chain of the further plurality of scan chains having an associated output circuitry responsive to a leading edge of the further punched-out clock, the scan chains of the further plurality of scan chains being connected to the compacting logic.

6. A circuit arrangement according to claim 1 , further comprising:
a pattern generation circuitry comprising a pseudo-random pattern generator and a sequential pattern retiming element;
the pseudo-random pattern generator being operable at the second punched-out clock, the pseudo-random pattern generator having an output circuitry responsive to a leading edge of the second punched-out clock;
each scan chain having an associated input circuitry responsive to a leading edge of the first punched-out clock;
the sequential pattern retiming element being connected with its inputs to the output circuitry of the pseudo-random pattern generator and connected with its outputs to the input circuitry of the associated scan chains;
the sequential pattern retiming element being operable at the second punched-out clock, the inputs of the sequential pattern retiming element being responsive to a trailing edge of the second punched-out clock.

7. A circuit arrangement according to claim 1 , wherein the cycle time of the first punched-out clock and the cycle time of the second punched-out clock correspond to an even number of system clock periods and the delay corresponds to half of the even number of system clock periods.

8. A circuit arrangement according to claim 7 , wherein the even number is 2, 4, 6 or 8.

9. A circuit arrangement according to claim 1 , wherein the cycle time of the first punched-out clock and the cycle time of the second punched-out clock correspond to an odd number of system clock periods, the odd number being equal or larger than three, and the delay corresponds to half of the odd number minus one of system clock periods or half of the odd number plus one of system clock periods.

10. A circuit arrangement according to claim 1 , wherein
the output circuitry of the scan chains comprises a first leading-edge triggered D-flip-flop for being responsive to the leading edge of the first punched-out clock,
the sequential retiming element comprises a trailing-edge triggered D-flip-flop for being responsive to the trailing edge of the second punched-out clock, and
the input circuitry of the Multi-Input Signature Register comprises a second leading-edge triggered D-flip-flop for being responsive to the leading edge of the second punched-out clock.

11. A semiconductor device comprising a circuit arrangement according to claim 1 .

12. A method of operating a circuit arrangement for Logic Built-In Self-Test of a semiconductor device claim 1 , the method comprising:
operating a clock source to generate a system clock having a system clock pulse duration and a system clock period;
operating first clock division circuitry to derive a first punched-out clock from the system clock by periodically suppressing one or more successive clock pulses of the system clock to obtain the first punched-out clock having a pulse duration corresponding to the system clock pulse duration and a cycle time corresponding to a plurality of system clock periods;
operating a plurality of scan chains at the first punched-out clock, each scan chain having an associated output circuitry responsive to a leading edge of the first punched-out clock;
operating second clock division circuitry to derive a second punched-out clock from the system clock by periodically suppressing one or more successive clock pulses of the system clock to obtain the second punched-out clock with a pulse duration corresponding to the system clock pulse duration and a cycle time corresponding to the cycle time of the first punched-out clock, the second punched-out clock having a delay of one or more system clock periods relative to the first punched-out clock;
receiving signals from the output circuitries of the plurality of scan chains at its inputs and compacting the signals provided into a compacted output;

Assignees

• Ahrens Heiko
• Latzel Claudia
• Richter Bernhard
• Freescale Semiconductor Inc

Inventors

• Ahrens Heiko
• Latzel Claudia
• Richter Bernhard

Classifications

• G01R31/3187

  Built-in tests · CPC title

• G01R31/318547 Primary

  Data generators or compressors · CPC title

• G01R31/318575

  Power distribution; Power saving · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title