Oscillator devices and methods

US9444468B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9444468-B2
Application numberUS-201314138290-A
CountryUS
Kind codeB2
Filing dateDec 23, 2013
Priority dateDec 23, 2013
Publication dateSep 13, 2016
Grant dateSep 13, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Oscillator devices and corresponding methods are disclosed. In some embodiments an apparatus includes an oscillator circuit arrangement, a frequency variable resistor circuit coupled to an output of the oscillator circuit arrangement and a reference resistor circuit. The apparatus further includes a sample and hold circuit, wherein a first input of the sample and hold circuit is coupled to an output of the reference resistor circuit and a second input of the sample and hold circuit is coupled to an output of the frequency variable resistor circuit, wherein an output of the sample and hold circuit is coupled with an input of the oscillator circuit arrangement.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: an oscillator circuit arrangement; a frequency variable resistor circuit coupled to an output of the oscillator circuit arrangement; a reference resistor circuit; and a sample and hold circuit, a first input of the sample and hold circuit being coupled to an output of the reference resistor circuit and a second input of the sample and hold circuit being coupled to an output of the frequency variable resistor circuit, wherein an output of the sample and hold circuit is coupled with an input of the oscillator circuit arrangement, and wherein the sample and hold circuit is configured to sample signals received at the first and second inputs at specific sampling points in time and to output sampled values with essentially constant values until a respective next sampling point. 2. The apparatus of claim 1 , wherein the oscillator circuit arrangement comprises a controllable oscillator, wherein the oscillator circuit arrangement is configured to control a frequency of the controllable oscillator based on the output of the sample and hold circuit. 3. The apparatus of claim 2 , wherein the output of the sample and hold circuit comprises a first output to output a first sampled signal based on a first signal received from the frequency variable resistor circuit and a second output to output a second sampled signal based on a second signal output from the reference resistor circuit, wherein the oscillator circuit arrangement is configured to control the controllable oscillator based on a difference between the first sampled signal and the second sampled signal. 4. The apparatus of claim 2 , wherein the output of the sample and hold circuit comprises a first output and a second output, wherein the oscillator circuit arrangement comprises an operational transconductance amplifier, a first input of the operational transconductance amplifier being coupled with the first output of the sample and hold circuit and a second input of the operational transconductance amplifier being coupled with the second output of the sample and hold circuit, and an output of the operational transconductance amplifier being coupled with an input of the controllable oscillator. 5. The apparatus of claim 4 , wherein the controllable oscillator comprises a current controlled oscillator. 6. The apparatus of claim 1 , wherein the output of the oscillator circuit arrangement is coupled with a clock input of the sample and hold circuit. 7. The apparatus of claim 1 , wherein the oscillator circuit arrangement comprises a clock divider, wherein an output of the clock divider is coupled with an input of the frequency variable resistor circuit. 8. The apparatus of claim 1 , wherein the frequency variable resistor circuit comprises a current source and a frequency variable resistor coupled in series between a first supply voltage and a second supply voltage, wherein the output of the frequency variable resistor circuit is tapped at a node between the current source and the frequency variable resistor. 9. The apparatus of claim 1 , wherein a frequency variable resistor of the frequency variable resistor circuit comprises a switch, the switch being controlled by an output signal of the oscillator circuit arrangement. 10. The apparatus of claim 1 , wherein a frequency variable resistor of the frequency variable resistor circuit comprises: a first capacitance; a second capacitance; a pair of first switches; and a pair of second switches, wherein, when the pair of first switches is closed and the pair of second switches is opened, a first terminal of the first capacitance is coupled with a first terminal of the second capacitance and a second terminal of the first capacitance is coupled with a second terminal of the second capacitance, and wherein, when the first pair of switches is opened and when the second pair of switches is closed, the first terminal of the first capacitance is coupled with the second terminal of the second capacitance and the second terminal of the first capacitance is coupled with the first terminal of the second capacitance. 11. An apparatus comprising: a reference resistor circuit; a frequency variable resistor circuit; and an oscillator circuit arrangement comprising a controllable oscillator and being configured to control a frequency of the controllable oscillator based on an output of the reference resistor circuit and the frequency variable resistor circuit, wherein the frequency variable resistor circuit is coupled to an output of the oscillator circuit arrangement, wherein the frequency variable resistor circuit comprises a first capacitance, a second capacitance, a first pair of switches and a second pair of switches, the first pair of switches and the second pair of switches being controlled by different phases of a first output signal of the oscillator circuit arrangement, wherein, when the first pair of switches is closed and the second pair of switches is open, a first terminal of the first capacitance is coupled with a first terminal of the second capacitance and a second terminal of the first capacitance is coupled with a second terminal of the second capacitance, and wherein, when the first pair of switches is open and the second pair of switches is closed, the first terminal of the first capacitance is coupled with the second terminal of the second capacitance and the second terminal of the first capacitance is coupled with the first terminal of the second capacitance. 12. The apparatus of claim 11 , wherein a switch of the first pair of switches or the second pair of switches comprises a T-gate switch. 13. The apparatus of claim 11 , further comprising a sample and hold circuit coupled between the reference resistor circuit and the oscillator circuit arrangement and between the frequency variable resistor circuit and the oscillator circuit arrangement. 14. The apparatus of claim 13 , wherein the sample and hold circuit is controlled by a second output signal of the oscillator circuit arrangement such that sampling occurs at an end of a control period of the frequency variable resistor circuit. 15. A method comprising: providing a first signal from a reference resistor circuit and a second signal from a frequency variable resistor circuit to a sample and hold circuit; providing a sampled first signal and a sampled second signal from the sample and hold circuit to an oscillator circuit arrangement; and providing an output signal of the oscillator circuit arrangement to the frequency variable resistor circuit, wherein providing the sampled first signal and the sampled second signal to the oscillator circuit arrangement comprises providing the sampled first signal from the first signal and the sampled second signal form the second signal at specific sampling points in time with essentially constant values until a respective next sampling point. 16. The method of claim 15 , further comprising controlling a sampling of the sample and hold circuit to be at an end of a period of the output signal provided to the frequency variable resistor circuit. 17. The method of claim 15 , further comprising controlling a controllable oscillator of the oscillator circuit arrangement based on a difference between the first sampled signal and the second sampled signal. 18. The method of claim 17 , wherein the oscillator circuit arrangement is a current controlled oscillator, and the controlling comprises generating a control current based on a difference between the first sampled signal and the second sampled signal.

Assignees

Inventors

Classifications

  • using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

  • Astable circuits {(H03K3/0315 takes precedence)} · CPC title

  • H03L7/06Primary

    using a reference signal applied to a frequency- or phase-locked loop · CPC title

  • H03L7/00Primary

    Automatic control of frequency or phase; Synchronisation · CPC title

  • using a frequency discriminator comprising a passive frequency-determining element · CPC title

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What does patent US9444468B2 cover?
Oscillator devices and corresponding methods are disclosed. In some embodiments an apparatus includes an oscillator circuit arrangement, a frequency variable resistor circuit coupled to an output of the oscillator circuit arrangement and a reference resistor circuit. The apparatus further includes a sample and hold circuit, wherein a first input of the sample and hold circuit is coupled to an o…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H03L7/06. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).