Circuit and method for powering an integrated circuit having first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels

Patent metadata

Field	Value
Publication number	US-9444456-B2
Application number	US-201113187274-A
Country	US
Kind code	B2
Filing date	Jul 20, 2011
Priority date	Jul 20, 2011
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Power supply is facilitated. In accordance with one or more embodiments, a power regulator circuit includes first and second regulators and a controller for controlling operation of the power regulator circuit in standby and normal operational modes. The first and second regulators respectively provide regulated power at main and standby power levels, the standby power level being lower than the main power level. For the standby mode, the controller operates the second regulator for supplying power to an integrated circuit at the standby power level. For transitioning to the normal mode, the controller turns the first regulator on while continuing to operate the second regulator for supplying power to the integrated circuit during a start-up period. After a start-up period (e.g., when the first regulator is up to full power), the controller operates the first regulator for supplying power for operating the processor in a high-frequency mode.

First claim

What is claimed is:

1. A power regulator circuit comprising:
first and second power regulators respectively configured and arranged to provide regulated power to an integrated circuit at main and standby power levels and to provide regulated power to internal power rails for powering less than all of the power regulator circuit which includes a first circuit, the standby power level being less than half of the main power level; and
a controller circuit configured and arranged to
in a standby mode, output a standby signal to operate the second power regulator for supplying power to an integrated circuit at the standby power level and to cause the first power regulator, and the first circuit, to be in an off mode in which the first power regulator is directed to consume no current and in which power via the internal power rails is not provided to the first circuit, thereby limiting power consumed by the integrated circuit at the standby power level;
transition from the standby mode to a startup mode, output a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and output a start signal for operating a processor circuit in the integrated circuit in a low-frequency mode, and
after the start-up period, operating the first power regulator for supplying power at the main power level for operating the processor circuit in a high-frequency mode.

2. The circuit of claim 1 , wherein, in the startup mode,
the controller circuit is configured to output a signal for operating an oscillator to drive the processor circuit in the low-frequency mode,
the second power regulator is configured to provide the regulated power to the oscillator for operating the oscillator at low frequency to drive the processor circuit in the low-frequency mode, and
the controller circuit is configured to, in response to the first power regulator providing a threshold power level, control the first power regulator to provide the regulated power to the oscillator for operating the oscillator at a high frequency to power the processor circuit in a high-frequency mode.

3. The circuit of claim 1 , wherein the controller circuit is configured and arranged
with circuitry to operate the second power regulator in the standby mode, and to operate both the first and second power regulators simultaneously during the start-up period in response to an external stimulus, and for providing a signal for causing an oscillator to start driving the processor circuit in the low frequency mode and switching an oscillator to the high-frequency mode after the start-up period, and
to monitor the power level of the first power regulator and, in response to the first power regulator providing power at a power threshold, terminate the startup mode by turning the second power regulator off and controlling the first power regulator for supplying the power for operating the processor circuit in the high-frequency mode.

4. The circuit of claim 1 , wherein the controller circuit is configured and arranged to output the startup signal to control the first power regulator for entering the startup mode from the standby mode in response to receiving a request for accessing the integrated circuit, and wherein the first circuit is configured and arranged to provide a clock signal coupled to drive the processor circuit.

5. The circuit of claim 1 , wherein the controller circuit is configured and arranged to, in response to receiving a request for accessing the integrated circuit,
output a control signal to control the second power regulator for supplying power to the integrated circuit, and output the start signal for operating the processor circuit in the low-frequency mode to serve the request, and
after the request has been served, output the standby signal to operate the second power regulator for supplying power to the integrated circuit at the standby power level, and outputting a control signal for turning the processor circuit off.

6. The circuit of claim 1 , wherein the controller circuit is configured and arranged to, in the startup mode, operate the second power regulator for supplying power to the integrated circuit at a startup power level that is higher than the standby power level.

7. The circuit of claim 1 , wherein the second power regulator is configured and arranged for supplying power to the integrated circuit in the startup mode at a power level that is higher than the standby power level, to operate the processor circuit in the low-frequency mode.

8. The circuit of claim 1 , wherein the controller circuit is configured to output a control signal to power off a plurality of circuits, including a circuit other than the first power regulator and the first circuit, in the integrated circuit for entering the standby mode, thereby causing the first power regulator to be in the off mode.

9. The circuit of claim 1 , wherein the controller circuit is configured to output the standby and startup signals by outputting a status signal indicative of the respective standby and startup modes.

10. The circuit of claim 1 , wherein the controller circuit is configured to output the start signal for operating a processor circuit in the integrated circuit in a low-frequency mode by outputting a signal to operate a clock generation circuit to oscillate at low frequency for operating the processor circuit.

11. A power regulator circuit comprising:
first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power level; and
a controller circuit configured and arranged to
in a standby mode, output a standby signal to operate the second power regulator for supplying power to an integrated circuit at the standby power level,
transition from the standby mode to a startup mode, output a startup signal to turn the first power regulator on while continuing to operate the second power regulator for supplying power to the integrated circuit during a start-up period, and output a start signal for operating a processor circuit in the integrated circuit in a low-frequency mode, and
after the start-up period, operating the first power regulator for supplying power at the main power level for operating the processor circuit in a high-frequency mode, wherein, in the standby mode, the controller circuit is configured and arranged with the first power regulator to operate that first power regulator in an off mode in which the first power regulator is directed to consume no current;

in the startup mode,
the controller circuit is configured to output a signal for operating an oscillator to drive the processor circuit in the low-frequency mode using power from the second power regulator, and
the second power regulator is configured and arranged to provide regulated power to the oscillator at a startup power level until the start-up period has ended and the first power regulator is operating at the main power level; and

the controller circuit includes circuitry configured and arranged to operate the oscillator at the high-frequency using power from the first power regulator at the end of the start-up period, and to disable the second power regulator after the start-up period while the first power regulator powers the oscillator for providing the main power level.

12. A method for powering an integrated circuit having first and second power regulators respectively configured and arranged to provide regulated power at main and standby power levels, the standby power level being less than half of the main power

Assignees

• Robertson Peter
• Gunther Andre
• Mahooti Kevin
• Nxp Bv

Inventors

• Robertson Peter
• Gunther Andre
• Mahooti Kevin

Classifications

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title