Current sense circuit using a single opamp having DC offset auto-zeroing

Patent metadata

Field	Value
Publication number	US-9444414-B2
Application number	US-201414329615-A
Country	US
Kind code	B2
Filing date	Jul 11, 2014
Priority date	Jul 11, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A current sense circuit having a single opamp DC offset auto-zero capability that allows for continuous current sensing operation while at the same time providing for DC offset sensing and compensation. The single opamp design can operate in a first phase to sense and store a DC offset, while providing an output to drive an output stage of the current sense circuit. The single opamp design can operate in a second phase, using the sensed DC offset to generate an accurate output that can drive the output stage and which can be used in the first phase.

First claim

I claim the following:

1. A circuit comprising:
first and second circuit inputs;
a circuit output;
a first capacitor;
a second capacitor connected to the circuit output;
a third capacitor;
an amplifier having first and second amplifier inputs and an amplifier output; and
a plurality of switches operable to be in a first configuration and operable to be in a second configuration,
wherein, in the first configuration of the switches:
the amplifier output is disconnected from the circuit output;
the first capacitor is connected across the amplifier inputs to sense a DC offset of the amplifier; and
the second capacitor is connected only between the circuit output and one of the circuit inputs; and
the third capacitor is connected only to the first and second circuit inputs,

wherein, in the second configuration of the switches:
the amplifier output is connected to the circuit output;
the first capacitor is connected to one of the amplifier inputs to compensate for the DC offset of the amplifier; and
the second capacitor is connected to the amplifier in a feedback loop.

2. The circuit of claim 1 further comprising wherein in the second configuration of the switches, the third capacitor is connected to both the second capacitor and the amplifier to integrate a charge of the third capacitor onto the second capacitor using the amplifier.

3. The circuit of claim 1 wherein, in both the first configuration of the switches and the second configuration of the switches, one of the circuit inputs is connected to provide a voltage reference point that is common to the first capacitor, the second capacitor, and the amplifier.

4. The circuit of claim 1 wherein, in the first configuration of the switches, the first capacitor is connected between one of the amplifier inputs and one of the circuit inputs.

5. The circuit of claim 1 wherein the first circuit input is connected to a first transistor and the second circuit input is connected to a second transistor.

6. The circuit of claim 5 wherein the first transistor and the second transistor are connected in a current mirror configuration.

7. The circuit of claim 1 wherein the circuit output is connected to an output stage comprising a first transistor.

8. The circuit of claim 7 wherein the first transistor is connected with a second transistor as a cascode.

9. The circuit of claim 7 wherein the first transistor is connected with a second transistor as a current mirror.

10. A circuit comprising:
first and second circuit inputs;
a circuit output;
an amplifier having an output, the output having a first configuration that is not connected to the circuit output and a second configuration that is connected to the circuit output;
an output capacitor that is connected to the circuit output, the output capacitor having a first configuration that is connected to the amplifier in a feedback loop and a second configuration that is not connected to the amplifier;
an input capacitor that is connected to the first circuit input, the input capacitor having a first configuration that is connected to the amplifier in a feedback loop with the output capacitor and a second configuration that is connected to only the second circuit input; and
a first offset capacitor having a first configuration that is connected to first and second inputs of the amplifier and having a second configuration that is connected in series with the input capacitor at a time when the input capacitor is connected to the amplifier in the feedback loop with the output capacitor,
wherein at a time when the amplifier is in the first configuration, the output capacitor is in the first configuration, the input capacitor is in the first configuration, and the offset capacitor is in the first configuration.

11. The circuit of claim 10 further comprising a plurality of switches that are connected to the amplifier, the output capacitor, the input capacitor, and the offset capacitor, each switch being selectively operable to an open position and to a closed position.

12. The circuit of claim 11 further comprising one or more control inputs to receive control signals to operate the switches.

13. The circuit of claim 10 further comprising a plurality of switches that are operable to configure the amplifier in the first configuration, the output capacitor in the first configuration, the input capacitor in the first configuration, and the offset capacitor in the first configuration, and to configure the amplifier in the second configuration, the output capacitor in the second configuration, the input capacitor in the second configuration, and the offset capacitor in the second configuration.

14. The circuit of claim 10 further comprising a second offset capacitor that is configured to be disconnected from the first offset capacitor at a time when the first offset capacitor is in the first configuration, and to be connected in parallel with the first offset capacitor at a time when the first offset capacitor is in the second configuration.

15. The circuit of claim 10 wherein at a time when the amplifier is in the second configuration, the output capacitor is in the second configuration, the input capacitor is in the second configuration, and the offset capacitor is in the second configuration.

16. The circuit of claim 10 wherein the amplifier comprises a single opamp.

17. A circuit comprising:
a pass transistor having an output terminal connectable to a load;
a sense transistor connected to the pass transistor to mirror a current flow through the pass transistor;
an output stage connected to the sense transistor; and
an amplifier circuit having a first circuit input connected to the pass transistor, a second circuit input connected to the sense transistor, and a circuit output connected to the output stage, the amplifier circuit comprising:
an amplifier section having an output that is selectively connectable to and disconnectable from the circuit output;
an integrator section connected to the circuit output and selectively connectable to and disconnectable from the amplifier section; and
an offset nulling section connected to the amplifier section,
wherein the amplifier section is disconnected from the circuit output at a time when the offset nulling section is sampling an offset of the amplifier, and
wherein the integrator section stores a voltage difference between the first and second circuit inputs of the amplifier circuit and provides an output to the circuit output to drive the output stage at a time when the amplifier section is disconnected from the circuit output.

18. The circuit of claim 17 wherein the amplifier section is connected to the circuit output to drive the output stage at a time when the integrator section is connected to the amplifier section in a feedback loop configuration.

19. The circuit of claim 18 wherein the offset nulling section compensates a DC offset of the amplifier section using a sampled DC offset when the integrator section is connected to the amplifier section.

20. The circuit of claim 17 wherein the output stage comprises a transistor connected to the sense transistor as a cascode.

21. The circuit of claim 17 wherein the output stage comprises a current mirror.

22. The circuit of claim 17 wherein the pass transistor further having a control input connectable to a control source.

23. The circuit of claim 22 wherein the control source is an error amplifier of a low dropout regulator.

Assignees

• Qualcomm Inc

Inventors

• Peluso Vincenzo

Classifications

• H03F1/303 Primary

  using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title

• H03F2200/231

  the input of an amplifier can be switched on or off by a switch to amplify or not an input signal · CPC title

• H03F3/005 Primary

  using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence) · CPC title

• H03F2203/45156

  At least one capacitor being added at the input of a dif amp · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title