Antenna swap architectures for time-division duplexing communication systems
US-2016365908-A1 · Dec 15, 2016 · US
US2016352289A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016352289-A1 |
| Application number | US-201615073897-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 18, 2016 |
| Priority date | May 29, 2015 |
| Publication date | Dec 1, 2016 |
| Grant date | — |
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A front end circuit includes a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal.
Opening claim text (preview).
What is claimed is: 1 . A front end circuit, comprising: a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal. 2 . The front end circuit of claim 1 , wherein the bypass circuit further comprises a reducer connected in series between the first bypass switch and the second bypass switch. 3 . The front end circuit of claim 1 , wherein one end of the first bypass switch is connected to a second terminal, one end of the second bypass switch is connected to the other end of the first bypass switch and the other end of the second bypass switch is connected to the first terminal. 4 . The front end circuit of claim 1 , wherein the bypass circuit further comprises a reducer, wherein one end of the first bypass switch is connected to a second terminal, one end of the reducer is connected to the other end of the first bypass switch, the reducer being configured to reduce the signal, one end of the second bypass switch is connected to the other end of the reducer, and the other end of the second bypass switch is connected to the first terminal. 5 . The front end circuit of claim 4 , wherein the reducer comprises: a first resistor, one end of which is connected to the other end of the first bypass switch and the other end of the first resistor being connected to the one end of the second bypass switch; a second resistor, one end of which is connected to the one end of the first resistor and the other end of which is grounded; and a third resistor, one end of which is connected to the other end of the first resistor and the other end of which is grounded. 6 . The front end circuit of claim 1 , wherein the first bypass switch and the second bypass switch are configured to receive the same switching control signal to responsively perform the switching operations. 7 . The front end circuit of claim 1 , wherein the first bypass switch and the second bypass switch are configured to match input and/or output impedance of the bypass circuit to about 50 ohms. 8 . The front end circuit of claim 7 , wherein each of the first bypass switch and the second bypass switch comprise a stacked plurality of intercoupled switches. 9 . The front end circuit of claim 1 , wherein the amplifier comprises: a first amplifying switch, one end of which is connected to a second terminal configured to receive the signal; an amplifying part, one end of which is connected to the other end of the first amplifying switch, the amplifying part being configured to amplify the signal; and a second amplifying switch, one end of which is connected to the other end of the amplifying part and the other end of the second amplifying switch being connected to the first terminal. 10 . The front end circuit of claim 1 , wherein the amplifier comprises: a first amplifying switch, one end of which is connected to a second terminal configured to receive the signal; a first amplifying part, a gate terminal of which is connected to an other end of the first amplifying switch, and a source terminal of the first amplifying part being grounded; a second amplifying part, a source terminal of which is connected to a drain terminal of the first amplifying switch, and a drain terminal of the second amplifying part being connected to the first terminal; and a second amplifying switch, one end of which is connected to an other end of the second amplifying part and the other end of which is connected to the first terminal. 11 . The front end circuit of claim 9 , wherein the first and second amplifying switches are configured to match input and/or output impedance of the amplifying part to about 50 ohms. 12 . The front end circuit of claim 1 , further comprising a transmission and reception switch, one end of which is connected to a second terminal and the other end of which is connected to the amplifier and the bypass circuit. 13 . The front end circuit of claim 12 , wherein the transmission and reception switch is configured to maintain an ON state when the front end circuit performs a reception operation. 14 . A front end circuit, comprising: a bypass circuit configured to bypass a signal to a first terminal; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal, wherein the amplifier comprises a first amplifying switch and a second amplifying switch configured to amplify the signal according to switching operations of the first amplifying switch and the second amplifying switch. 15 . The front end circuit of claim 14 , wherein the amplifier further comprises an amplifying part configured to amplify the signal, wherein one end of the first amplifying switch is connected to a second terminal, one end of the amplifying part is connected to the other end of the first amplifying switch, one end of the second amplifying switch is connected to the other end of the amplifying part and the other end of the second amplifying switch is connected to the first terminal. 16 . The front end circuit of claim 14 , wherein the amplifier further comprises a first amplifying part and a second amplifying part, wherein one end of the first amplifying switch is connected to a second terminal, a gate terminal of the first amplifying part is connected to the other end of the first amplifying switch, a source terminal of the first amplifying part is connected to ground, a source terminal of the second amplifying part is connected to a drain terminal of the first amplifying part, a drain terminal of the second amplifying part is connected to the first terminal, one end of the second amplifying switch is connected to the other end of the second amplifying part, and the other end of the second amplifying switch is connected to the first terminal. 17 . A method of controlling a front end circuit comprising: identifying a signal strength of a signal; and, responsive to the identified signal strength, selectively: adapting an impedance by selective engagement of a network of switches; and, actuating an amplifier to amplify the signal; or, actuating a bypass circuit to omit amplification of the signal. 18 . The method of controlling a front end circuit of claim 17 , further comprising: receiving the signal from an antenna; and, executing a controller coupled to the amplifier and the bypass circuit to: identify the signal strength of the signal; and, selectively route the signal to the bypass circuit or the amplifier for output to an output port. 19 . The method of controlling a front end circuit of claim 17 , further comprising: receiving the signal from a controller; and, executing the controller coupled to the amplifier and the bypass circuit to: identify the signal strength of the signal; and, selectively route the signal to the bypass circuit or the amplifier for output to an antenna for wireless transmission to a wireless receiver. 20 . The method of controlling a front end circuit of claim 17 , wherein the network of switches are substantially simultaneously actuated responsive to a common switching signal generated by the controller.
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Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation · CPC title
the input of an amplifier can be switched on or off by a switch to amplify or not an input signal · CPC title
using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title
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