Semiconductor Device Comprising a Field Electrode

Patent metadata

Field	Value
Publication number	US-2016013280-A1
Application number	US-201514748712-A
Country	US
Kind code	A1
Filing date	Jun 24, 2015
Priority date	Jul 14, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A semiconductor device includes a gate electrode adjacent to a body region in a semiconductor substrate. The semiconductor device further includes a field electrode in a field plate trench in the main surface, the field plate trench having an extension length in a first direction parallel to a main surface. The extension length is less than the double of an extension length in a second direction that is perpendicular to the first direction parallel to the main surface. The extension length in the first direction is more than half of the extension length in the second direction. The field electrode is insulated from an adjacent drift zone by means of a field dielectric layer. A field plate material of the field electrode has a resistivity in a range from 10 5 to 10 −1 Ohm·cm.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a gate electrode adjacent to a body region in a semiconductor substrate; and a field electrode in a field plate trench in a main surface of the semiconductor substrate, the field plate trench having an extension length in a first direction parallel to the main surface, the extension length being less than the double of an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface, the extension length in the first direction being more than half of the extension length in the second direction, the field electrode being insulated from an adjacent drift zone by means of a field dielectric layer, wherein a field plate material of the field electrode has a resistivity in a range from 10 5 to 10 −1 Ohm·cm.

2 . The semiconductor device according to claim 1 , further comprising a source region adjacent to the main surface and a drain region adjacent to a back side surface opposing the main surface.

3 . The semiconductor device according to claim 2 , further comprising a source plate arranged over the field plate trench.

4 . The semiconductor device according to claim 1 , wherein the field plate material is selected from the group consisting of: polysilicon doped at a doping concentration between 1E16 cm −3 and 1E19 cm −3 , semi-insulating polysilicon (SIPOS) and amorphous silicon carbide.

5 . A semiconductor device comprising:
a gate electrode adjacent to a body region in a semiconductor substrate; and a field electrode in a field plate trench in a main surface of the semiconductor substrate, the field plate trench extending at the main surface and being electrically coupled to a source terminal at a plurality of positions; and a contact plug for electrically coupling the field electrode to a terminal, the contact plug comprising a contact material having a resistivity in a range from 10 5 to 10 −1 Ohm·cm.

6 . The semiconductor device according to claim 5 , wherein the field electrode comprises a field plate material having a resistivity less than 1E−1 Ohm·cm.

7 . The semiconductor device according to claim 6 , wherein the field plate material comprises a metal or doped polysilicon having a doping concentration of more than 1E20 cm −3 .

8 . The semiconductor device according to claim 5 , further comprising a source region adjacent to the main surface and a drain region adjacent to a back side surface opposing the main surface.

9 . The semiconductor device according to claim 5 , wherein the gate electrode is disposed in a gate trench and the gate trench and the field plate trench are merged to form a single trench.

10 . The semiconductor device according to claim 5 , wherein the contact material is selected from the group consisting of: polysilicon doped at a doping concentration between 1E16 cm −3 and 1E19 cm −3 , semi-insulating polysilicon (SIPOS) and amorphous silicon carbide.

11 . A semiconductor device comprising:
a gate electrode adjacent to a body region in a semiconductor substrate; and a field electrode in a field plate trench in a main surface of the semiconductor substrate, the field plate trench having an extension length in a first direction, the extension length being less than the double of an extension length in a second direction that is parallel to the main surface and perpendicular to the first direction, the extension length in the first direction being more than half of the extension length in the second direction; and a contact plug for electrically coupling the field electrode to a terminal, the contact plug comprising a contact material having a resistivity between 10 5 to 10 −1 Ohm·cm.

12 . The semiconductor device according to claim 11 , wherein the contact material is selected from the group consisting of: polysilicon doped at a doping concentration between 1E16 cm −3 ad 1E19 cm −3 , semi-insulating polysilicon (SIPOS), and amorphous silicon carbide.

13 . The semiconductor device according to claim 1 ,
wherein the gate electrode is disposed in a gate trench.

14 . The semiconductor device according to claim 1 ,
wherein the gate electrode is a planar gate electrode disposed over the main surface of the semiconductor substrate.

15 . A synchronous rectification device comprising the semiconductor device according to claim 1 .

16 . A power supply comprising the synchronous rectification device according to claim 15 .

Assignees

• Infineon Technologies Austria

Inventors

• Laforet David
• Hirler Franz
• Blank Oliver
• Siemieniec Ralf

Classifications

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/118

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title