System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks

Patent metadata

Field	Value
Publication number	US-9443053-B2
Application number	US-201314141096-A
Country	US
Kind code	B2
Filing date	Dec 26, 2013
Priority date	Dec 26, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution network. The instance name includes (X,Y) coordinate information corresponding to placement of the macrocell in the physical layout of the network design. Base cells in each macrocell are placed in a known deterministic arrangement, such as one on top of another in a layout of the clock distribution network, all at the same (X,Y) offset. Preferably, the base cells are all from a standard-cell library, thereby reducing design cost and debug.

First claim

We claim:

1. A method of generating macrocells of a semiconductor device according to an integrated circuit design including a hybrid tree mesh clock distribution network, the method comprising:
generating with a computing device and storing on a non-transitory computer-readable medium, a collection of macrocells instantiated in the integrated circuit design, wherein instance names of the macrocells include placement information for placing the macrocells in a layout of the integrated circuit design, and further wherein each of the macrocells includes one or more corresponding base cells;
determining target drive strengths of clock signals for multiple sequential components on the semiconductor device;
determining groups of standard-size clock-driving elements, wherein each of the standard-size clock-driving elements corresponds to one of the base cells and each of the groups has a drive strength equal to one of the target drive strengths;
combining the clock-driving elements into the groups;
extracting with the computing device, from each of the instance names of the macrocells on the non-transitory computer-readable medium, the corresponding placement information; and
distributing the clock signals having the target drive strengths on the semiconductor device with the groups of clock-driving elements as the groups form the hybrid tree mesh clock distribution network of the semiconductor device.

2. The method of claim 1 , further comprising placing the macrocells on the semiconductor device of the integrated circuit based on the placement information.

3. The method of claim 2 , wherein placing the macrocells comprises, for each of the macrocells, placing the base cells of the macrocell at fixed locations relative to each other based on the corresponding placement information.

4. The method of claim 3 , wherein the placement information comprises (X,Y) coordinates, and the fixed locations are fixed locations from the (X,Y) coordinates.

5. The method of claim 4 , wherein the fixed locations are in a same row of a layout of the integrated circuit design.

6. The method of claim 4 , wherein the fixed locations are in different rows of a layout of the integrated circuit design.

7. The method of claim 4 , wherein the fixed locations in both a same and different rows of a layout of the integrated circuit design.

8. The method of claim 5 , wherein the macrocells form clock stations on a clock-distribution network.

9. The method of claim 8 , wherein the clock-distribution network comprises the hybrid tree-mesh clock-distribution network.

10. The method of claim 9 , wherein the placement information further comprises a level number corresponding to a level of a macrocell in a clock station of the clock-distribution network.

11. The method of claim 1 , wherein the base cells comprises inverters, buffers, integrated clock-driving cells, complex logic functions, or any combination thereof.

12. The method of claim 1 , wherein drive strengths of the standard-size clock-driving elements comprise 8×, 12×, and 16×, and drive strengths of the groups range from 0× to 64×.

13. A method of placing macrocells of a semiconductor device according to an integrated circuit design including a hybrid tree mesh clock distribution network, the method comprising:
generating with a computing device and storing on a non-transitory computer-readable medium, a collection of macrocells instantiated in the integrated circuit design, wherein instance names of the macrocells include placement information for placing the macrocells in a layout of the integrated circuit design, and further wherein each of the macrocells includes one or more corresponding base cells;
extracting with the computing device, from each of the instance names of the macrocells on the non-transitory computer-readable medium, the corresponding placement information;
placing the macrocells of the non-transitory computer-readable medium with the computing device based on the placement information;
determining target drive strengths of clock signals for multiple sequential components on the semiconductor device;
determining combinations of standard-size clock-driving elements, wherein each of the standard-size clock-driving elements corresponds to one of the base cells, each of the groups having a group drive strength equal to a sum of the drive strengths of the clock-driving elements in the group, each of the group drive strengths substantially equal to one of the target drive strengths;
combining the clock-driving elements into the groups; and
distributing the clock signals having the target drive strengths on the semiconductor device with the groups of clock-driving elements as the groups form the hybrid tree mesh clock distribution network of the semiconductor device.

14. A non-transitory computer-readable medium, the medium comprising:
computer executable instructions which when executed by computing device perform a method of controlling placement of base cells of a collection of macrocells on a semiconductor device according to an integrated circuit design including a hybrid tree mesh clock distribution network, the method comprising:
generating the collection of the macrocells instantiated in the integrated circuit design, wherein instance names of the macrocells include placement information for placing the macrocells in a layout of the integrated circuit design;
determining target drive strengths of clock signals for multiple sequential components on the semiconductor device;
extracting the placement information from the instance names of the macrocells;
grouping standard-size clock-driving elements into groups such that clock signal drive strengths of each of the groups corresponds to one of the target drive strengths of the multiple sequential components on the semiconductor device, wherein each of the standard-size clock-driving elements corresponds to one of the base cells; and
distributing the clock signals having the target drive strengths on the semiconductor device with the groups as the groups form the hybrid tree mesh clock distribution network of the semiconductor device.

15. The computer-readable medium of claim 14 , wherein the method further comprises placing the base cells in pre-determined relative arrangement on the semiconductor device of an integrated circuit based on the placement information.

16. The computer-readable medium of claim 15 , wherein the placement information comprises an (X,Y) coordinate.

17. The computer-readable medium of claim 16 , wherein the pre-determined relative arrangement comprises pre-determined locations relative to the (X,Y) coordinate.

18. The computer-readable medium of claim 17 , wherein the locations are all in a single column of a layout of the integrated circuit.

19. The computer-readable medium of claim 14 , wherein the computer executable instructions are further configured to generate physical routes to connect input pins and output pins of the base cells.

20. The computer-readable medium of claim 19 , wherein the computer executable instructions are further configured to mark first and second terminals and to couple all input pins of the base cells to the first terminal and to couple all output pins of the base cells to the second terminal according to connectivity in a netlist.

21. The computer-readable medium of claim 20 , wherein the computer executable instructions are further configured to balance lengths of the routes to maintain skew in the integrated circuit within a pre-determine

Assignees

• Xpliant Inc
• Cavium Inc

Inventors

• Jayakumar Nikhil
• Trivedi Vivek
• Palisetti Vasant K
• Mula Bhagavati R
• Ahluwalia Daman
• Motamedi Amir H

Classifications

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F17/5009

  Physics · mapped topic

• G06F17/5072

  Physics · mapped topic

• G06F17/5077 Primary

  Physics · mapped topic

• G06F2217/62

  Physics · mapped topic