Accessing data stored in a command/address register device

Patent metadata

Field	Value
Publication number	US-9442871-B2
Application number	US-201113995477-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

First claim

What is claimed is:

1. In a memory subsystem, a method comprising:
logging information about a memory command in a register device coupled to a dynamic random access memory (DRAM) device over an address bus of the memory subsystem, the register device not coupled to a data bus of the memory subsystem;
detecting a read trigger for the log information in the register device; and
in response to detecting the read trigger, writing the log information to a multipurpose register (MPR) of the DRAM device, the MPR to make the log information accessible to a host processor over the data bus.

2. The method of claim 1 , wherein the register device performs memory command parity error checking, and wherein logging the information comprises logging parity error information into the register device, and wherein detecting the read trigger further comprises stopping the memory command at the register device and not sending the command to the DRAM device.

3. The method of claim 1 , wherein logging the information comprises logging debugging information in the register device.

4. The method of claim 1 , wherein the register device comprises a Mode Register, and wherein logging the information comprises writing Mode Register configuration in the register device to be read out over the data bus in response to a read trigger.

5. The method of claim 1 , wherein detecting the read trigger comprises detecting a command from a memory controller that includes both address and command information to trigger writing from the register device as a source to the MPR as a destination.

6. The method of claim 1 , wherein writing the log information to the MPR further comprises including an MPR selection code in a read trigger command.

7. The method of claim 1 , wherein the address bus comprises an address or command bus.

8. An article of manufacture comprising a non-transitory computer-readable storage medium having content stored thereon, which when executed in a memory subsystem cause the memory subsystem to perform operations including:
logging information about a memory command in a register device coupled to a dynamic random access memory (DRAM) device over an address bus of the memory subsystem, the register device not coupled to a data bus of the memory subsystem;
detecting a read trigger for the log information in the register device; and
in response to detecting the read trigger, writing the log information to a multipurpose register (MPR) of the DRAM device, the MPR to make the log information accessible to a host processor over the data bus.

9. The article of manufacture of claim 8 , wherein the register device performs memory command parity error checking, and wherein the content for performing logging the information comprises content for performing logging parity error information into the register device, and wherein the content for performing detecting the read trigger further comprises content for performing stopping the memory command at the register device and not sending the command to the DRAM device.

10. The article of manufacture of claim 8 , wherein the content for performing logging the information comprises content for performing logging debugging information in the register device.

11. The article of manufacture of claim 8 , wherein the register device comprises a Mode Register, and wherein the content for performing logging the information comprises content for performing writing Mode Register configuration in the register device to be read out over the data bus in response to a read trigger.

12. The article of manufacture of claim 8 , wherein the content for performing detecting the read trigger comprises content for performing detecting a command from a memory controller that includes both address and command information to trigger writing from the register device as a source to the MPR as a destination.

13. The article of manufacture of claim 8 , wherein the content for performing writing the log information to the MPR further comprises content for performing providing an MPR selection code in a read trigger command.

14. A memory subsystem, comprising:
a multipurpose register (MPR) of a dynamic random access memory (DRAM) device, the MPR being writeable via an address bus of the memory subsystem and readable via a data bus of the memory subsystem; and
a register device coupled to the MPR on the address bus and not coupled to a data bus of the memory subsystem, to log information about a memory command, and write the log information to the MPR in response to a read trigger received at the register device to make the log information accessible at the MPR,
wherein a host processor coupled to the memory subsystem is to read the log information from the MPR over the data bus.

15. The memory subsystem of claim 14 , wherein the register device is further to perform memory command parity error checking and log parity error information, and is further to stop the memory command at the register device instead of sending the command to the DRAM device.

16. The memory subsystem of claim 14 , wherein the register device is to log debugging information.

17. The memory subsystem of claim 14 , wherein the register device comprises a Mode Register, and wherein the Mode Register is to log Mode Register configuration to be read out over the data bus in response to a read trigger.

18. The memory subsystem of claim 14 , wherein the read trigger comprises a command from a memory controller that includes both address and command information to trigger writing from the register device as a source to the MPR as a destination.

19. The memory subsystem of claim 14 , wherein the register device is to write the log information to the MPR in accordance with an MPR selection code in a read trigger command.

20. The memory subsystem of claim 14 , wherein the register device is coupled between a memory controller and the DRAM device on the address bus, wherein all communication sent from the memory controller to the DRAM device on the address bus goes through the register device.

Assignees

• Bains Kuljit S
• Ruff Klaus J
• Vergis George
• Sah Suneeta
• Intel Corp

Inventors

• Bains Kuljit S
• Ruff Klaus J
• Vergis George
• Sah Suneeta

Classifications

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F11/1612

  where the redundant component is persistent storage · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title