Interrupted write memory operation in a serial interface memory with a portion of a memory address

Patent metadata

Field	Value
Publication number	US-9442867-B2
Application number	US-201414171630-A
Country	US
Kind code	B2
Filing date	Feb 3, 2014
Priority date	Nov 16, 2010
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Subject matter disclosed herein relates to read and write processes of a memory device.

First claim

What is claimed is:

1. An electronically-implemented method of accessing memory, the method comprising:
receiving a read command including a first portion of a memory address of a memory device, wherein the first portion of the memory address identifies a memory partition of the memory device, wherein the first portion is less than all of the memory address, wherein the memory address is received serially;
determining that a write operation is being performed in the same memory partition, starting a process of interrupting the write operation prior to receiving all of the memory address;
storing a memory address of the write operation responsive to the process of interrupting the write operation;
reading contents of the memory partition at the memory address;
retrieving the stored memory address of the write operation subsequent to reading the contents of the memory partition; and
resuming the write operation based at least in part on the retrieved stored memory address of the write operation.

2. The method of claim 1 , further comprising initiating internal sensing operations to read the contents of the memory partition prior to receiving all of the memory address.

3. The method of claim 1 , wherein interrupting the write operation is initiated by an internal microcontroller in the memory device.

4. The method of claim 1 , wherein the memory device comprises a phase change memory (PCM).

5. The method of claim 1 , wherein the write operation is initiated by an internal operation of the memory device.

6. The method of claim 1 , wherein the resuming the write operation is initiated by an internal microcontroller in the memory device.

7. The method of claim 1 , wherein each partition includes its own read circuitry and/or row and column decode circuitry.

8. A microcontroller of a memory device comprising:
at least one interface to connect to a memory array; and
electronic circuitry configured to:
receive a read command including a first portion of a memory address of the memory array, wherein the first portion of the memory address identifies a memory partition of the memory device, wherein the first portion is less than all of the memory address, wherein the memory address is received serially;
determining that a write operation is being performed in the same memory partition, start

a process to interrupt the write operation prior to receiving all of the memory address;
store a memory address of the write operation responsive to the process of interrupting the write operation;
read contents of the memory partition at the memory address;
retrieve the stored memory address of the write operation subsequent to reading the contents of the memory partition; and
resume the write operation based at least in part on the retrieved stored memory address of the write operation.

9. The microcontroller of the memory device of claim 8 , further comprising an electronic circuit configured to initiate internal sensing operations to read the contents of the memory partition prior to receiving a final portion of the memory address.

10. The microcontroller of the memory device of claim 8 , wherein interruption of the write operation is initiated by the microcontroller in the memory device.

11. The microcontroller of the memory device of claim 8 , wherein the resumption of the write operation is initiated by the microcontroller in the memory device.

12. The microcontroller of the memory device of claim 8 , wherein the memory device comprises a serial phase change memory (PCM).

13. The microcontroller of the memory device of claim 8 , wherein each partition includes its own read circuitry and/or row and column decode circuitry.

14. A system comprising:
a memory device comprising a memory array, the memory device further comprising a microcontroller configured to:
receive a read command including a first portion of a memory address of the memory array, wherein the first portion of the memory address identifies a memory partition of the memory device, wherein the first portion is less than all of the memory address, wherein the memory address is received serially;
determining that a write operation is being performed in the same memory partition, start a process to interrupt the write operation prior to receiving all of the memory address;
store a memory address of the write operation responsive to the process of interrupting the write operation;
read contents of the memory partition at the memory address;
retrieve the stored memory address of the write operation subsequent to reading the contents of the memory partition; and
resume the write operation based at least in part on the retrieved stored memory address of the write operation; and

a processor configured to host one or more applications and configured to initiate the read command to the microcontroller to provide access to the memory array.

15. The system of claim 14 , wherein the microcontroller is adapted to initiate internal sensing operations to read the contents of the memory partition prior to receiving a final portion of the memory address.

16. The system of claim 14 , wherein interruption of the write operation is initiated by the microcontroller.

17. The system of claim 14 , wherein the resumption of the write operation is initiated by the microcontroller.

18. The system of claim 14 , wherein the memory device comprises a serial phase change memory (PCM).

19. The system of claim 14 , wherein each partition includes its own read circuitry and/or row and column decode circuitry.

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Vimercati Daniele

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C5/066

  Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title

• G11C2207/2209

  Concurrent read and write · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title