Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same

Patent metadata

Field	Value
Publication number	US-9437809-B2
Application number	US-201414290477-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	Jan 12, 2009
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

First claim

What is claimed is:

1. A memory cell comprising:
a pinned ferromagnetic layer;
a nonmagnetic source layer formed on the pinned ferromagnetic layer;
an insulative layer formed on the nonmagnetic source layer, wherein the insulative layer comprises a thickness in the range of approximately 10-30 nm;
a free ferromagnetic layer formed on the insulative layer; and
nanochannels formed in the insulative layer, wherein each of the nanochannels is filled with a filament contact comprising material from the nonmagnetic source layer.

2. The memory cell of claim 1 , wherein the filament contact is configured to decrease a cross sectional area of a programming current flow.

3. The memory cell of claim 1 , comprising an access transistor electrically coupled to the memory cell and configured to provide electrical access to the memory cell.

4. The memory cell of claim 3 , comprising a word line coupled to a gate of the access transistor.

5. The memory cell of claim 1 , comprising a bit line coupled to the memory cell.

6. The memory cell of claim 3 , comprising a source line coupled to a source or a drain of the access transistor.

7. The memory cell of claim 1 , wherein each of the nanochannels and filament contacts have random shapes.

8. The memory cell of claim 1 , wherein the nonmagnetic source layer comprises copper or silver.

9. A memory cell comprising:
a pinned layer;
a nonmagnetic source layer formed on the pinned layer;
an insulative layer formed on the nonmagnetic source layer, wherein the insulative layer comprises a thickness in the range of approximately 10-30 nm;
a free layer formed on the insulative layer; and
a filament contact formed from the nonmagnetic source layer and formed through the insulative layer such that the filament contact is electrically coupled between the pinned layer and the free layer.

10. The memory cell of claim 9 , wherein the filament contact is non-uniform.

11. The memory cell of claim 9 , wherein the nonmagnetic source layer comprises a thickness in the range of approximately 5-15 nm.

12. The memory cell of claim 9 , wherein the insulative layer comprises SiN or SiC.

13. The memory cell of claim 9 , wherein the insulative layer comprises a chalcogenide material.

14. The memory cell of claim 9 , wherein the pinned layer comprises one of Co, Fe, Ni or its alloys, NiFe, CoFe, CoNiFe, or doped alloys CoX, CoFeX, CoNiFeX (X=B, Cu, Re, Ru, Rh, Hf, Pd, Pt, C), or Fe3O4, CrO2, NiMnS, PtMnSb, or BiFeO.

15. The memory cell of claim 9 , wherein the free layer comprises one of Co, Fe, Ni or its alloys, NiFe, CoFe, CoNiFe, or doped alloys CoX, CoFeX, CoNiFeX (X=B, Cu, Re, Ru, Rh, Hf, Pd, Pt, C), or Fe3O4, CrO2, NiMnS, PtMnSb, or BiFeO.

16. The memory cell of claim 9 , wherein the nonmagnetic source layer comprises copper or silver.

17. A memory cell comprising:
a pinned layer;
a free layer;
an insulative layer formed between the pinned layer and the free layer, wherein the insulative layer comprises a thickness in the range of approximately 10-30 nm; and
a filament contact formed through the insulative layer such that the filament contact is electrically coupled between the pinned layer and the free layer, wherein the filament contact comprises a random shape.

18. The memory cell of claim 17 , comprising a nonmagnetic source layer formed between the pinned layer and the free layer.

19. The memory cell of claim 18 , wherein the filament contact is formed from the nonmagnetic source layer.

20. The memory cell of claim 18 , wherein the nonmagnetic source layer has a thickness in the range of approximately 5-15 nm.

21. The memory cell of claim 17 , comprising an antiferromagnetic layer directly adjacent to the pinned layer.

Assignees

• Micron Technology Inc

Inventors

• Liu Jun
• Sandhu Gurtej

Classifications

• H01F10/3268

  the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn · CPC title

• H01F41/307

  insulating or semiconductive spacer · CPC title

• H01F10/329

  Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title

• H01L43/08 Primary

  Electricity · mapped topic

• H01F41/306

  conductive spacer · CPC title