Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9437696-B2
Application number	US-201314056697-A
Country	US
Kind code	B2
Filing date	Oct 17, 2013
Priority date	May 31, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on both ends of the gate electrode, wherein a pin is formed under the gate electrode between the active regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including an element isolation region;
a trench formed in the element isolation region;
a gate electrode buried in the trench; and
a plurality of active regions formed under the gate electrode,
wherein the element isolation region has an upper surface and a bottom surface of a fin structure formed under the gate electrode between two adjacent active regions, and
wherein the gate electrode includes a first region and a second region, the first region of the gate electrode is directly contacted to the upper surface of the fin structure included in the element isolation region, and the second region of the gate electrode is directly contacted to the bottom surface of the fin structure included in the element isolation region.

2. The semiconductor device of claim 1 , wherein the upper surface of the fin structure is higher than a bottom surface of the trench.

3. The semiconductor device of claim 1 , wherein the fin structure includes an insulating material.

4. The semiconductor device of claim 1 , wherein the first region has a first thickness and the second region has a second thickness thicker than the first thickness.

5. A semiconductor device, comprising:
a substrate having an element isolation region;
a trench formed in the element isolation region;
a gate electrode buried in the trench; and
a plurality of active regions formed under the gate electrode,
wherein the element isolation region is formed on the gate electrode and includes a fin structure formed under the gate electrode between two adjacent active regions, and
wherein the gate electrode includes a first region and a second region, the first region of the gate electrode is directly contacted to an upper surface of the fin structure included in the element isolation region, and the second region of the gate electrode is directly contacted to a bottom surface of the fin structure included in the element isolation region.

6. The semiconductor device of claim 5 , wherein the upper surface of the fin structure is higher than a bottom surface of the trench.

7. The semiconductor device of claim 5 , wherein the first region has a first thickness and the second region has a second thickness thicker than the first thickness.

8. The semiconductor device of claim 5 , wherein the gate electrode includes a metal.

9. The semiconductor device of claim 5 , wherein each of the active regions has a bar shape having a long axis and a short axis, and ends of the long axis of neighboring active regions are adjacent to each other.

10. A semiconductor device, comprising:
a substrate having an element isolation region;
a first trench formed in the element isolation region;
a first gate electrode buried in the first trench;
a plurality of active regions formed under the first gate electrode;
a second trench formed in the element isolation region and in parallel to the first trench; and
a second gate electrode buried in the second trench,
wherein the element isolation region is formed under the first gate electrode between two adjacent active regions and includes a fin structure formed protrudedly on a bottom surface of the first trench, and
wherein the first gate electrode includes a first region and a second region, the first region is disposed over an upper surface of the fin structure included in the element isolation region, and the second region is disposed over a bottom surface of the fin structure included in the element isolation region.

11. The semiconductor device of claim 10 , wherein the first region of the first gate electrode has a first thickness and the second region of the first gate electrode has a second thickness thicker than the first thickness.

12. The semiconductor device of claim 10 , wherein the gate electrode includes a metal.

13. The semiconductor device of claim 10 , wherein each of the active regions has a bar shape having a long axis and a short axis, and ends of the long axis of neighboring active regions are adjacent to each other.

14. A semiconductor device, comprising:
a substrate having an element isolation region and an active region defined by the element isolation region;
trenches formed in the active region and the element isolation region; and
a gate electrode buried in the trenches,
wherein the trenches have a same depth in the active region and the element isolation region, and
wherein the element isolation region have a fin structure formed under the gate electrode between two adjacent active regions, and
wherein the gate electrode includes a first region and a second region, the first region of the gate electrode is directly contacted to an upper surface of the fin structure included in the element isolation region, and the second region of the gate electrode is directly contacted to a bottom surface of the fin structure included in the element isolation region.

15. The semiconductor device of claim 14 , wherein the bottom surface of the fin structure is formed on a bottom surface of the trench in the element isolation region, and
wherein the upper surface of the fin structure extends protrudedly from the bottom surface of the fin structure.

Assignees

• Sk Hynix Inc

Inventors

• Kim Ji-In
• Kim Do-Youn

Classifications

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title