High-quality GaN high-voltage HFETs on silicon

US9437688B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9437688-B2
Application numberUS-201514834192-A
CountryUS
Kind codeB2
Filing dateAug 24, 2015
Priority dateDec 9, 2011
Publication dateSep 6, 2016
Grant dateSep 6, 2016

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Abstract

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A GaN HFET includes a silicon substrate with an Al 2 O 3 layer above the silicon substrate. The Al 2 O 3 layer has voids formed therein. A plurality of alternating GaN and AlN layers are above the Al 2 O 3 layer. The GaN and AlN layers are under continuous compressive stress.

First claim

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What is claimed is: 1. A GaN HFET, comprising: a silicon substrate; an Al 2 O 3 layer above the silicon substrate, the Al 2 O 3 layer having voids formed therein; and a plurality of alternating GaN and AlN layers above the Al 2 O 3 layer, wherein the GaN and AlN layers are under continuous compressive stress. 2. The GaN HFET of claim 1 , further comprising an amorphous layer located between the silicon substrate and the Al 2 O 3 layer. 3. The GaN HFET of claim 1 , wherein the GaN layers in the plurality of alternating GaN and AlN layers have a minimum thickness of 500 nm. 4. The GaN HFET of claim 1 , wherein the GaN layers in the plurality of alternating GaN and AlN layers have a maximum thickness of 50,000 nm. 5. A method of making a GaN HFET comprising: forming an amorphous film of AlSiO between a silicon wafer and an Al 2 O 3 film on a surface of the silicon wafer; and depositing a plurality of alternating GaN and AlN layers above the Al 2 O 3 layer. 6. The method of claim 5 , further comprising forming voids in the Al 2 O 3 film on a top surface of a silicon wafer, wherein the top surface of the silicon wafer is along a <111> silicon crystal orientation, and wherein the voids are filled with AlN and GaN. 7. The method of claim 6 , wherein said forming the voids includes exposing portions of the amorphous film of AlSiO along a bottom of the voids.

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What does patent US9437688B2 cover?
A GaN HFET includes a silicon substrate with an Al 2 O 3 layer above the silicon substrate. The Al 2 O 3 layer has voids formed therein. A plurality of alternating GaN and AlN layers are above the Al 2 O 3 layer. The GaN and AlN layers are under continuous compressive stress.
Who is the assignee on this patent?
Power Integrations Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/2905. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).