Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar
US-2024419761-A1 · Dec 19, 2024 · US
US9437656B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9437656-B2 |
| Application number | US-201414515205-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 15, 2014 |
| Priority date | Mar 24, 2010 |
| Publication date | Sep 6, 2016 |
| Grant date | Sep 6, 2016 |
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A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.
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What is claimed is: 1. A semiconductor memory device, comprising: a first, a second, a third and a fourth bit line extending in a first direction; a first, a second, a third and a fourth electrode arranged in a second direction intersecting the first direction; a fifth electrode extending in the second direction; a first dielectric film having a first surface and a second surface being opposite to the first surface, the first, second, third and fourth electrodes provided to…
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