Semiconductor device and method of forming insulating layer around semiconductor die

Patent metadata

Field	Value
Publication number	US-9437552-B2
Application number	US-201414449869-A
Country	US
Kind code	B2
Filing date	Aug 1, 2014
Priority date	Mar 9, 2010
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
depositing an encapsulant between the semiconductor die;
designating a singulation area between the semiconductor die;
forming an insulating layer over the encapsulant in the singulation area;
forming a double channel in the insulating layer in the singulation area while leaving a portion of the encapsulant in the singulation area covered by the insulating layer; and
singulating the semiconductor die through the insulating layer and encapsulant in the singulation area after forming the double channel, the singulation area being devoid of conductive material.

2. The method of claim 1 , wherein the insulating layer reduces outgassing from the encapsulant.

3. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
designating a singulation area between the semiconductor die;
forming an insulating layer including a first portion of the insulating layer over the singulation area and a second portion of the insulating layer between a first semiconductor die of the plurality of semiconductor die and a substrate edge;
forming an opening in the first portion of the insulating layer while retaining a part of the first portion of the insulating layer over the singulation area;
singulating the semiconductor die through the second portion of the insulating layer; and
singulating the semiconductor die through the first portion of the insulating layer after forming the opening, the singulation area being devoid of conductive material.

4. The method of claim 3 , further including depositing an encapsulant between the semiconductor die.

5. The method of claim 3 , further including forming a channel in the insulating layer around the semiconductor die.

6. The method of claim 3 , further including forming a double channel in the insulating layer around the semiconductor die.

7. The method of claim 3 , further including forming a net pattern in the insulating layer around the semiconductor die.

8. The method of claim 3 , further including forming a rectangular waveform pattern in the insulating layer around the semiconductor die.

9. A semiconductor device, comprising:
a plurality of semiconductor die;
an encapsulant deposited between the semiconductor die including a portion of the encapsulant designated as a saw street, the saw street devoid of conductive material; and
an insulating layer formed over a first portion of the saw street with a second portion of the saw street devoid of the insulating layer, the insulating layer including a rectangular waveform pattern around the semiconductor die.

10. The semiconductor device of claim 9 , further including a channel in the insulating layer around the semiconductor die.

11. The semiconductor device of claim 9 , further including a double channel in the insulating layer around the semiconductor die.

12. The semiconductor device of claim 9 , further including a net pattern in the insulating layer around the semiconductor die.

13. The semiconductor device of claim 9 , wherein the insulating layer reduces outgassing from a molding area of the encapsulant.

14. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited around the semiconductor die including a portion of the encapsulant designated as a saw street, the saw street devoid of conductive material; and
an insulating layer formed over a first portion of the saw street with a second portion of the saw street devoid of the insulating layer, the insulating layer including a double channel around the semiconductor die.

15. The semiconductor device of claim 14 , further including a net pattern in the insulating layer around the semiconductor die.

16. The semiconductor device of claim 14 , further including a rectangular waveform pattern in the insulating layer around the semiconductor die.

17. The semiconductor device of claim 14 , further including an opening formed in the insulating layer over the saw street.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chen Kang
• Fang Jianmin
• Feng Xia
• Bao Xusheng

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/01257

  by reflowing · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title