Mask-less dual silicide process

Patent metadata

Field	Value
Publication number	US-9437495-B2
Application number	US-201414542264-A
Country	US
Kind code	B2
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain regions and second source/drain regions in a second device region. A silicide treatment is performed on the second source/drain regions while the mask layer protects the first source/drain regions. The mask layer is then removed and a silicide treatment is performed on the first source/drain regions.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first gate stack in a first device region of a substrate and a second gate stack in a second device region of the substrate, first source/drain regions being on opposing sides of the first gate stack, second source/drain regions being on opposing sides of the second gate stack;
oxidizing the first source/drain regions, thereby forming a mask layer along a surface of the first source/drain regions;
forming a patterned dielectric layer over the first device region and the second device region, the first source/drain regions and the second source/drain regions being exposed through the patterned dielectric layer;
forming a second silicide layer over the second source/drain regions;
removing the mask layer; and
forming a first silicide layer over the first source/drain regions.

2. The method of claim 1 , the forming the mask layer comprises:
forming one or more first masking layers over the first device region and the second device region; and
patterning the first masking layers in the first device region to form first spacers alongside the first gate stack.

3. The method of claim 1 , wherein the oxidizing comprises implanting oxygen.

4. The method of claim 1 , wherein the first gate stack and the second gate stack are dummy gate stacks.

5. The method of claim 1 , further comprising removing the first gate stack and the second gate stack and forming a first metal gate stack and a second metal gate stack.

6. The method of claim 1 , further comprising forming first stress regions in the first source/drain regions.

7. The method of claim 6 , further comprising forming second stress regions in the second source/drain regions.

8. A method of forming a semiconductor device, the method comprising:
providing a substrate, the substrate having a first device region and a second device region, the first device region having a first gate stack, the second device region having a second gate stack, first source/drain regions being on opposing sides of the first gate stack, second source/drain regions being on opposing sides of the second gate stack;
forming first stress regions in the first source/drain regions;
forming first oxidized regions in the first source/drain regions;
forming second stress regions in the second source/drain regions;
forming a first dielectric layer over the first device region and the second device region;
patterning the first dielectric layer to expose the first oxidized regions and the second stress regions;
forming second silicide regions over the second stress regions;
after forming the second silicide regions, removing the first oxidized regions; and
forming first silicide regions over the first stress regions.

9. The method of claim 8 , further comprising forming one or more layers over the second device region prior to the forming the first oxidized regions.

10. The method of claim 9 , further comprising, after the forming the first oxidized regions, patterning the one or more layers over the second device region to form first spacers alongside the second gate stack.

11. The method of claim 10 , further comprising:
forming an additional dielectric layer over the first device region and the second device region; and
patterning the additional dielectric layer over the second device region to form additional spacers alongside the second gate stack;
wherein the additional dielectric layer protects the first oxidized regions during the forming the second stress regions.

12. The method of claim 8 , wherein the removing the first oxidized regions comprises a SiCoNi clean process.

13. The method of claim 8 , wherein the forming the first oxidized regions comprises implanting oxygen.

14. A method of forming a semiconductor device, the method comprising:
forming a first gate stack in a first device region of a substrate and a second gate stack in a second device region of the substrate, first source/drain regions being on opposing sides of the first gate stack, second source/drain regions being on opposing sides of the second gate stack;
forming a first mask layer over the second device region;
forming first stress regions in the first source/drain regions;
oxidizing a surface of the first stress regions while the first mask layer protects the second source/drain regions, thereby forming first oxidized regions;
removing a portion of the first mask layer over the second source/drain regions;
forming second stress regions in the second source/drain regions;
forming an interlayer dielectric (ILD) over the first device region and the second device region, the ILD being patterned to expose the first oxidized regions and the second stress regions;
forming a second silicide region in the second source/drain regions;
removing at least a portion of the first oxidized regions; and
forming a first silicide region in the first source/drain regions.

15. The method of claim 14 , wherein the first mask layer comprises a plurality of layers.

16. The method of claim 14 , further comprising, after the oxidizing, patterning the first mask layer over the second device region to form first spacers alongside the second gate stack.

17. The method of claim 16 , further comprising:
forming an additional dielectric layer over the first device region and the second device region; and
patterning the additional dielectric layer over the second device region to form additional spacers alongside the second gate stack;
wherein the additional dielectric layer protects the first oxidized regions during the forming the second stress regions and the second silicide regions.

18. The method of claim 14 , wherein the removing at least a portion of the first oxidized regions comprises a SiCoNi clean process.

19. The method of claim 14 , wherein the forming the first oxidized regions comprises implanting oxygen.

20. The method of claim 14 , further comprising replacing the first gate stack and the second gate stack with metal gate stacks.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chen-Ming
• Yang Fu-Kai
• Wang Hsien-Cheng
• Wang Mei-Yun

Classifications

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title