Processing method for wafer having chamfered portion along the outer circumference thereof followed by thinning and separating

US9437439B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9437439-B2
Application numberUS-201213666365-A
CountryUS
Kind codeB2
Filing dateNov 1, 2012
Priority dateNov 8, 2011
Publication dateSep 6, 2016
Grant dateSep 6, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wafer processing method for reducing the thickness of a wafer to a predetermined thickness, the wafer having a chamfered portion along the outer circumference thereof. The wafer processing method includes a stacked wafer forming step of attaching a support substrate to the front side of the wafer to thereby form a stacked wafer, and a chamfered portion removing step of positioning a cutting blade having a rotation axis parallel to the stacking direction of the stacked wafer formed by the stacked wafer forming step so that the outer circumference of the cutting blade faces the chamfered portion of the wafer, and then making the cutting blade cut into the wafer from the outer circumference toward the center thereof to thereby partially remove the chamfered portion in the range corresponding to the predetermined thickness from the front side of the wafer.

First claim

Opening claim text (preview).

What is claimed is: 1. A device wafer processing method for reducing the thickness of a device wafer to a predetermined thickness, said device wafer having a chamfered portion along the outer circumference thereof, said wafer processing method comprising: a stacked wafer forming step of attaching a support substrate to a front side of said device wafer to thereby form a stacked wafer followed by; a chamfered portion removing step of positioning a single cutting blade that is thinner in width than the device wafer, the single cutting blade having a rotation axis parallel to the stacking direction of said stacked wafer formed by said stacked wafer forming step so that the outer circumference of said single cutting blade faces said chamfered portion of said device wafer, and then making said single cutting blade cut into said device wafer without cutting into or damaging the support substrate from the outer circumference toward the center thereof to thereby remove said chamfered portion to at least said predetermined thickness from the front side of said device wafer; followed by thickness reducing step of grinding a back side of said device wafer constituting said stacked wafer after performing said chamfered portion removing step to thereby reduce the thickness of said device wafer to said predetermined thickness; followed by a separation step of removing said support substrate from said device wafer. 2. The device wafer processing method according to claim 1 , further comprising a holding step of holding said stacked wafer on a chuck table of a cutting apparatus in a condition where said support substrate of said stacked wafer comes into contact with said chuck table before performing said chamfered portion removing step; said chamfered portion removing step including the steps of: positioning said cutting blade so that the rotation axis of said cutting blade becomes parallel to the rotation axis of said chuck table and the outer circumference of said cutting blade faces said chamfered portion of said device wafer; making said cutting blade cut into said device wafer from the outer circumference toward the center thereof; and rotating said chuck table at least 360° during said chamfered portion removing step.

Assignees

Inventors

Classifications

  • used to protect an active side of a device or wafer · CPC title

  • used during dicing or grinding · CPC title

  • Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

  • using temporarily an auxiliary support · CPC title

  • located on the periphery of wafers, e.g. orientation notches or lot numbers · CPC title

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Frequently asked questions

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What does patent US9437439B2 cover?
A wafer processing method for reducing the thickness of a wafer to a predetermined thickness, the wafer having a chamfered portion along the outer circumference thereof. The wafer processing method includes a stacked wafer forming step of attaching a support substrate to the front side of the wafer to thereby form a stacked wafer, and a chamfered portion removing step of positioning a cutting b…
Who is the assignee on this patent?
Disco Corp
What technology area does this patent fall under?
Primary CPC classification H10P52/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).