Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference

Patent metadata

Field	Value
Publication number	US-9437320-B1
Application number	US-201514687267-A
Country	US
Kind code	B1
Filing date	Apr 15, 2015
Priority date	Apr 15, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A system including a receiving module to receive data from cells of memory, each cell storing multiple bits, each bit corresponding to a different type of page of the memory, the bits stored in a cell denoting a state of the cell, and the data including bits from a page of the memory or states of cells along a word line of the memory. A processor generates a reliability indication for a first portion of the data corresponding to a first cell based on the first portion of the data and one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell. A decoder decodes the first portion of the data based on the first portion of the data and the reliability indication for the first portion of the data.

First claim

What is claimed is:

1. A system comprising:
a receiving module configured to receive data from cells of memory, wherein each of the cells stores multiple bits, wherein each of the bits corresponds to a different type of page of the memory, wherein the bits stored in one of the cells denote a state of the one of the cells, and wherein the data includes (i) bits from a page of the memory or (ii) states of cells along a word line of the memory;
a processor configured to generate a reliability indication for a first portion of the data corresponding to a first cell based on (i) the first portion of the data and (ii) one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell; and
a decoder configured to decode the first portion of the data based on (i) the first portion of the data and (ii) the reliability indication for the first portion of the data.

2. The system of claim 1 , wherein the decoder is configured to decode the first portion of the data based on an additional reliability indication for the first portion of the data received from the memory.

3. The system of claim 1 , wherein in response to the data including bits from a page of the memory:
the first portion of the data includes a first bit corresponding to the first cell received from the page;
the one or more second portions of the data include one or more bits corresponding to the one or more of the cells received from the page; and
the processor is configured to generate the reliability indication for the first bit based on (i) the first bit and (ii) the one or more bits.

4. The system of claim 1 , wherein in response to the data including states of cells along a word line of the memory:
the first portion of the data includes a first state of the first cell along the word line;
the one or more second portions of the data includes one or more states of the one or more of the cells along the word line; and
the processor is configured to generate a plurality of bits as the reliability indication for each of the bits of the first state based on (i) the bits of the first state and (ii) corresponding bits of the one or more states.

5. The system of claim 1 , further comprising a selecting module configured to select the first portion and the one or more second portions of the data using a sliding window.

6. The system of claim 1 , wherein:
the decoder is configured to generate feedback based on decoding the first portion of the data;
the processor is configured to generate the reliability indication for the first portion of the data based on (i) the first portion and the one or more second portions of the data and (ii) the feedback; and
the decoder is configured to decode the first portion of the data based on ( 1 ) the first portion of the data and (ii) the reliability indication for the first portion of the data.

7. The system of claim 1 , wherein:
the decoder is configured to generate feedback based on decoding the first portion of the data;
the processor is configured to update the reliability indication for the first portion of the data based on the feedback; and
the decoder is configured to decode the first portion of the data based on (i) the first portion of the data and (ii) the updated reliability indication for the first portion of the data.

8. The system of claim 1 , wherein:
the processor is configured to generate a plurality of bits as reliability indications for bits of a first state of a first cell based on (i) the bits of the first state and (ii) corresponding bits of one or more states of the first cell that are adjacent to the first state of the first cell; and
the decoder is configured to decode the first state of the first cell based on (i) the first state of the first cell received from the data and (ii) the reliability indications for the bits of the first state of the first cell.

9. A method comprising:
receiving data from cells of memory, wherein each of the cells stores multiple bits, wherein each of the bits corresponds to a different type of page of the memory, wherein the bits stored in one of the cells denote a state of the one of the cells, and wherein the data includes (i) bits from a page of the memory or (ii) states of cells along a word line of the memory;
generating a reliability indication for a first portion of the data corresponding to a first cell based on (i) the first portion of the data and (ii) one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell; and
decoding the first portion of the data based on (i) the first portion of the data and (ii) the reliability indication for the first portion of the data.

10. The method of claim 9 , further comprising decoding the first portion of the data based on an additional reliability indication for the first portion of the data received from the memory.

11. The method of claim 9 , wherein in response to the data including bits from a page of the memory, the first portion of the data includes a first bit corresponding to the first cell received from the page, and the one or more second portions of the data include one or more bits corresponding to the one or more of the cells received from the page, the method further comprising generating the reliability indication for the first bit based on (i) the first bit and (ii) the one or more bits.

12. The method of claim 9 , wherein in response to the data including states of cells along a word line of the memory, the first portion of the data includes a first state of the first cell along the word line, and the one or more second portions of the data includes one or more states of the one or more of the cells along the word line, the method further comprising generating a plurality of bits as the reliability indication for each of the bits of the first state based on (i) the bits of the first state and (ii) corresponding bits of the one or more states.

13. The method of claim 9 , further comprising selecting the first portion and the one or more second portions of the data using a sliding window.

14. The method of claim 9 , further comprising:
generating feedback based on decoding the first portion of the data;
generating the reliability indication for the first portion of the data based on (i) the first portion and the one or more second portions of the data and (ii) the feedback; and
decoding the first portion of the data based on (i) the first portion of the data and (ii) the reliability indication for the first portion of the data.

15. The method of claim 9 , further comprising:
generating feedback based on decoding the first portion of the data;
updating the reliability indication for the first portion of the data based on the feedback; and
decoding the first portion of the data based on (i) the first portion of the data and (ii) the updated reliability indication for the first portion of the data.

16. The method of claim 9 , further comprising:
generating a plurality of bits as reliability indications for bits of a first state of a first cell based on (i) the bits of the first state and (ii) corresponding bits of one or more states of the first cell that are adjacent to the first state of the first cell; and
decoding the first state of the first cell based on (i) the first state of the first cell received from the data and (ii) the reliability indications for the bits of the first state of the first cell.

Assignees

• Marvell Int Ltd

Inventors

• Nguyen Phong Sy
• Chilappagari Shashi Kiran

Classifications

• G11C11/5621

  using charge storage in a floating gate · CPC title

• G11C16/349 Primary

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title