Semiconductor storage device with two control lines

Patent metadata

Field	Value
Publication number	US-9208826-B2
Application number	US-201314388436-A
Country	US
Kind code	B2
Filing date	Feb 27, 2013
Priority date	Mar 30, 2012
Publication date	Dec 8, 2015
Grant date	Dec 8, 2015

Abstract

Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction. The storage node is connected to a gate of a third transistor, and a current flowing between a drain and a source of the third transistor is controlled according to a voltage level of the storage node.

First claim

What is claimed is:

1. A semiconductor storage device, comprising:
a memory cell including a first transistor that is an oxide semiconductor insulated-gate field-effect transistor, a second transistor that is an oxide semiconductor insulated-gate field-effect transistor, and a capacitor; and
a third transistor,
wherein either one of a drain and a source of the first transistor is connected to one end of the capacitor, defining a storage node,
wherein another of the drain or the source of the first transistor is connected to one of a drain or a source of the second transistor,
wherein another of the drain or the source of the second transistor is a data input terminal,
wherein a first control terminal, defined by a connection between another end of the capacitor and either one of respective gates of the first transistor and the second transistor, is connected to a first control line extending in a first direction,
wherein a second control terminal that is another of the respective gates of the first transistor or the second transistor is connected to a second control line extending in a second direction that is perpendicular to the first direction, and
wherein the storage node between the first transistor and the capacitor is connected to a gate of the third transistor and controls a current flowing between a drain and a source of the third transistor according to a voltage level of the storage node.

2. The semiconductor storage device according to claim 1 , wherein the first transistor and the second transistor are thin film transistors formed on an insulating film formed over a surface of a semiconductor substrate where the third transistor is formed.

3. The semiconductor storage device according to claim 1 , wherein an oxide semiconductor that forms the first transistor and the second transistor is InGaZnO.

4. The semiconductor storage device according to claim 1 , comprising:
a memory cell array that has a plurality of said memory cells of claim 1 arranged in a matrix in the first direction and the second direction,
wherein each of said plurality of memory cells is provided with the third transistor as a transistor for reading data stored in the storage node between the first transistor and the capacitor,
wherein every row of memory cells in the memory cell array extending in the first direction shares the first control line extending in the first direction,
wherein every column of the memory cells in the memory cell array extending in the second direction shares the second control line extending in the second direction, and
wherein the data input terminals of the plurality of memory cells in each row in the first direction are connected to a shared data input line extending in the first direction, or the data input terminals of the plurality of memory cells in each column in the second direction are connected to a shared data input line extending in the second direction.

5. The semiconductor storage device according to claim 4 ,
wherein drains or sources of a plurality of the third transistors arranged in each column in the second direction are connected to a shared reading signal line extending in the second direction, and
wherein the data input terminals of the plurality of the memory cells arranged in each column in the second direction are connected to the data input line extending in the second direction, shared therebetween.

6. The semiconductor storage device according to claim 4 , wherein the third transistor is a transistor used in a reconfigurable logic circuit.

Assignees

• Sharp Kk

Inventors

• Yamauchi Yoshimitsu

Classifications

• G11C11/405 Primary

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G11C11/40

  using transistors · CPC title

• H01L27/1225

  Electricity · mapped topic