Semiconductor fabrication utilizing grating and trim masks

Patent metadata

Field	Value
Publication number	US-9436092-B2
Application number	US-201213712005-A
Country	US
Kind code	B2
Filing date	Dec 12, 2012
Priority date	Mar 30, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor device, said method comprising:
exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in said photoresist layer;
exposing said photoresist layer utilizing a trim mask having a chrome line in a blocking portion situated over a selected one of said unexposed lines, wherein said trim mask includes at least two recesses having different depths adjacent to said chrome line, and wherein said chrome line is aligned with respective sidewalls of said at least two recesses.

2. The method of claim 1 , further comprising developing said photoresist layer after said exposing said photoresist layer utilizing said trim mask.

3. The method of claim 1 , further comprising controlling a width of said unexposed lines by adjusting an exposure time of said photoresist layer while utilizing said grating mask.

4. The method of claim 1 , further comprising controlling a width of said unexposed lines by adjusting an exposure power for said photoresist layer while utilizing said grating mask.

5. The method of claim 1 , wherein said photoresist layer comprises a positive photoresist.

6. The method of claim 5 , further comprising etching a line into said semiconductor wafer where said selected one of said unexposed lines was blocked by said blocking portion of said trim mask.

7. The method of claim 1 , wherein said photoresist layer comprises a negative photoresist.

8. The method of claim 1 , wherein said grating mask comprises an alternating phase shift mask.

9. The method of claim 1 , wherein said grating mask comprises an alternating phase shift mask, said alternating phase shift mask comprising:
a chrome line to function as one of said plurality of grating lines;
a first recess having a first depth and situated adjacent to said chrome line;
a second recess having a second depth and situated adjacent to said chrome line on a side opposite of said first recess.

10. The method of claim 9 , wherein radiation passing through said first recess is approximately 180 degrees out of phase with radiation passing through said second recess.

11. A semiconductor wafer fabricated by a method comprising:
exposing a photoresist layer disposed on said semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in said photoresist layer;
exposing said photoresist layer utilizing a trim mask having a chrome line in a blocking portion situated over a selected one of said unexposed lines, wherein said trim mask includes at least two recesses having different depths adjacent to said chrome line, and wherein said chrome line is aligned with respective sidewalls of said at least two recesses.

12. The semiconductor wafer of claim 11 , wherein said photoresist layer is developed after said exposing said photoresist layer utilizing said trim mask.

13. The semiconductor wafer of claim 11 , wherein a width of said unexposed lines is controlled by adjusting an exposure time of said photoresist layer while utilizing said grating mask.

14. The semiconductor wafer of claim 11 , wherein a width of said unexposed lines is controlled by adjusting an exposure power for said photoresist layer while utilizing said grating mask.

15. The semiconductor wafer of claim 11 , wherein said photoresist layer comprises a positive photoresist.

16. The semiconductor wafer of claim 15 , wherein a line is etched into said semiconductor wafer where said selected one of said unexposed lines was blocked by said blocking portion of said trim mask.

17. The semiconductor wafer of claim 11 , wherein said photoresist layer comprises a negative photoresist.

18. The semiconductor wafer of claim 11 , wherein said grating mask comprises an alternating phase shift mask.

19. The semiconductor wafer of claim 11 , wherein said grating mask comprises an alternating phase shift mask, said alternating phase shift mask comprising:
a chrome line to function as one of said plurality of grating lines;
a first recess having a first depth and situated adjacent to said chrome line;
a second recess having a second depth and situated adjacent to said chrome line on a side opposite of said first recess.

20. The semiconductor wafer of claim 19 , wherein radiation passing through said first recess is approximately 180 degrees out of phase with radiation passing through said second recess.

Assignees

• Newport Fab Llc

Inventors

• Talor George
• Preisler Edward
• Howard David J

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• G03F7/203 Primary

  comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation · CPC title

• H01L29/06

  Electricity · mapped topic

• H01L22/12

  Electricity · mapped topic