Array substrate, driving method of array substrate, and display device

US9436044B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9436044-B2
Application numberUS-201414429105-A
CountryUS
Kind codeB2
Filing dateJul 30, 2014
Priority dateOct 9, 2013
Publication dateSep 6, 2016
Grant dateSep 6, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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Disclosed are an array substrate, a driving method of the array substrate, and a display device. The array substrate includes gate lines ( 12 ), data lines ( 11 ), and pixel units, each of the pixel units includes a common electrode ( 2, 3 ) and a pixel electrode ( 5 ). The common electrode ( 2, 3 ) includes a first common electrode ( 2 ) and a second common electrode ( 3 ). The first common electrode ( 2 ) includes a plurality of first strip electrodes and the second common electrode ( 3 ) includes a plurality of second strip electrodes. The first strip electrodes and the second strip electrodes are arranged alternately configured to form electrical fields with the pixel electrode ( 5 ) respectively. By disposing the first and second common electrodes forming multi-dimensional electric fields with the pixel electrode respectively, the transmittance of the display device is improved.

First claim

Opening claim text (preview).

What is claimed is: 1. An array substrate, comprising gate lines, data lines, and a plurality of pixel units defined by the gate lines and the data lines, each of the plurality pixel units comprising a common electrode and a pixel electrode, wherein the common electrode and the pixel electrode are located at different film layers and are insulated from each other by an insulating layer; the common electrode comprises a first common electrode connected to a first common electrode line and a second common electrode connected to a second common electrode line; the first common electrode and the second common electrode are both slit electrode and comprise a plurality of first strip electrodes and a plurality of second strip electrodes respectively; the first strip electrodes are arranged alternately with the second strip electrodes, configured to form electrical fields with the pixel electrode respectively. 2. The array substrate according to claim 1 , wherein the pixel electrode is a slit electrode and comprises a plurality of third strip electrodes; the third strip electrodes of the pixel electrode are arranged alternately with the first strip electrodes of the first common electrode and with the second strip electrodes of the second common electrode; the third strip electrodes of the pixel electrode are arranged alternatively between the first strip electrodes of the first common electrode and the second strip electrodes of the second common electrode that are adjacent to each other. 3. The array substrate according to claim 1 , wherein the first common electrode and the second common electrode are located at a same film layer; the first common electrode and the second common electrode both are located at a side of the pixel electrode that is away from a substrate of the array substrate, or, the first common electrode and the second common electrode both are located at a side of the pixel electrode that faces the substrate of the array substrate. 4. The array substrate according to claim 1 , wherein the first common electrode and the second common electrode are located at different film layers; the first common electrode and the second common electrode both are located at a side of the pixel electrode that is away from a substrate of the array substrate, or, the first common electrode and the second common electrode both are located at a side of the pixel electrode that faces the substrate of the array substrate, or, the first common electrode is located at a side of the pixel electrode that is away from a substrate of the array substrate and the second common electrode is located at a side of the pixel electrode that faces the substrate of the array substrate. 5. The array substrate according to claim 2 , wherein a distance between projections of the first strip electrodes of the first common electrode and the second strip electrodes of the second common electrode on the substrate, which are adjacent to each other, is larger than a width of the third strip electrodes of the pixel electrode. 6. The array substrate according to claim 2 , wherein a distance between the first strip electrodes of the first common electrode and the third strip electrodes of the pixel electrode in a direction parallel to the array substrate is 0˜0.6 μm; a distance between the second strip electrodes of the second common electrode and the third strip electrodes of the pixel electrode in a direction parallel to the array substrate is 0˜0.6 μm; and each of the first strip electrodes, the second strip electrodes and the third strip electrodes has a width of 2˜2.6 μm. 7. The array substrate according to claim 1 , wherein the pixel electrode is a plate electrode; the first common electrode and the second common electrode both are located at a same layer or different layers at a side of the pixel electrode that is away from a substrate of the array substrate. 8. A display device, comprising the array substrate of claim 1 . 9. A method of driving the array substrate of claim 1 , comprising: applying a first common voltage to the first common electrode through the first common electrode line; and applying a second common voltage to the second common electrode through the second common electrode line, wherein the second common voltage is different from the first common voltage; and providing a pixel voltage signal to the pixel electrode through the data line, wherein the pixel voltage signal is set between the first common voltage and the second common voltage. 10. The array substrate according to claim 2 , wherein the first common electrode and the second common electrode are located at a same film layer; the first common electrode and the second common electrode both are located at a side of the pixel electrode that is away from a substrate of the array substrate, or, the first common electrode and the second common electrode both are located at a side of the pixel electrode that faces the substrate of the array substrate. 11. The array substrate according to claim 2 , wherein the first common electrode and the second common electrode are located at different film layers; the first common electrode and the second common electrode both are located at a side of the pixel electrode that is away from a substrate of the array substrate, or, the first common electrode and the second common electrode both are located at a side of the pixel electrode that faces the substrate of the array substrate, or, the first common electrode is located at a side of the pixel electrode that is away from a substrate of the array substrate and the second common electrode is located at a side of the pixel electrode that faces the substrate of the array substrate. 12. The array substrate according to claim 11 , wherein the first common electrode and the second common electrode are located at different film layers; the first common electrode and the second common electrode both are located at a side of the pixel electrode that is away from a substrate of the array substrate, or, the first common electrode and the second common electrode both are located at a side of the pixel electrode that faces the substrate of the array substrate, or, the first common electrode is located at a side of the pixel electrode that is away from a substrate of the array substrate and the second common electrode is located at a side of the pixel electrode that faces the substrate of the array substrate. 13. The array substrate according to claim 3 , wherein a distance between projections of the first strip electrodes of the first common electrode and the second strip electrodes of the second common electrode on the substrate, which are adjacent to each other, is larger than a width of the third strip electrodes of the pixel electrode. 14. The array substrate according to claim 4 , wherein a distance between projections of the first strip electrodes of the first common electrode and the second strip electrodes of the second common electrode on the substrate, which are adjacent to each other, is larger than a width of the third strip electrodes of the pixel electrode. 15. The array substrate according to claim 12 , wherein a distance between projections of the first strip electrodes of the first common electrode and the second strip electrodes of the second common electrode on the substrate, which are adjacent to each other, is larger than a width of the third strip electrodes of the pixel electrode. 16. The array substrate according to claim 3 , wherein a distance between the first strip electrode of the first common electrode and the third strip electrode of the pixel electrode in a direction pa

Assignees

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Classifications

  • characterised by their geometrical arrangement · CPC title

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  • Generation of voltages supplied to electrode drivers · CPC title

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What does patent US9436044B2 cover?
Disclosed are an array substrate, a driving method of the array substrate, and a display device. The array substrate includes gate lines ( 12 ), data lines ( 11 ), and pixel units, each of the pixel units includes a common electrode ( 2, 3 ) and a pixel electrode ( 5 ). The common electrode ( 2, 3 ) includes a first common electrode ( 2 ) and a second common electrode ( 3 ). The first common el…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Beijing Boe Display Tech Co, Boe Technology Group Co Ltd, and 1 more
What technology area does this patent fall under?
Primary CPC classification G02F1/134309. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).