Integrated circuit (IC) test structure with monitor chain and test wires

Patent metadata

Field	Value
Publication number	US-9435852-B1
Application number	US-201514862587-A
Country	US
Kind code	B1
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.

First claim

We claim:

1. An integrated circuit (IC) test structure comprising:
a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level;
a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and
a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.

2. The IC test structure of claim 1 , wherein the first test wire comprises one of a plurality of first test wires positioned within the first metal level and extending in the first direction, and wherein each of the plurality of first test wires is electrically connected to a first spine wire extending in the second direction and positioned within the first metal level.

3. The IC test structure of claim 2 , wherein at least one of the plurality of first test wires is positioned laterally between two of the plurality of metal wires.

4. The IC test structure of claim 2 , wherein the second test wire comprises one of a plurality of second test wires positioned within the second metal level and extending in the second direction, and wherein each of the plurality of second test wires is electrically connected to a second spine wire extending in the first direction and positioned within the second metal level.

5. The IC test structure of claim 4 , wherein at least one of the plurality of second test wires is positioned laterally between two of the plurality of metal wires.

6. The IC test structure of claim 1 , further comprising a test pad electrically coupled to the monitor chain between the first end and the second end thereof.

7. The IC test structure of claim 1 , wherein each of the first and second test wires are free of vias electrically connected thereto.

8. The IC test structure of claim 1 , wherein at least one intervening metal level separates the first metal level from the second metal level.

9. An integrated circuit (IC) test structure comprising:
a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level;
a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and
a second test wire positioned within the second metal level and extending in a second direction, wherein the first direction is different from the second direction;
an interconnect via electrically coupled to one of the first test wire and the second test wire, and extending from the first metal level to the second metal level.

10. The IC test structure of claim 9 , wherein the first test wire comprises one of a plurality of first test wires positioned within the first metal level and extending in the first direction, and wherein each of the plurality of first test wires is electrically connected to a first spine wire extending in the second direction and positioned within the first metal level.

11. The IC test structure of claim 10 , wherein the interconnect via is electrically coupled to one of the plurality of first test wires, and positioned laterally between two of the plurality of test wires.

12. The IC test structure of claim 10 , wherein the interconnect via comprises one of a plurality of interconnect vias, each of the plurality of interconnect vias being coupled to one of the plurality of first test wires, and wherein at least one of the plurality of first test wires is free of interconnect vias electrically connected thereto.

13. The IC test structure of claim 10 , wherein at least one of the plurality of first test wires is positioned laterally between two of the plurality of metal wires.

14. The IC test structure of claim 10 , wherein the second test wire comprises one of a plurality of second test wires positioned within the second metal level and extending in the second direction, and wherein each of the plurality of second test wires is electrically connected to a second spine wire extending in the first direction and positioned within the second metal level.

15. The IC test structure of claim 9 , further comprising a test pad electrically coupled to the monitor chain between the first end and the second end thereof.

16. The IC test structure of claim 9 , wherein at least one intervening metal level separates the first metal level from the second metal level.

17. An integrated circuit (IC) test structure comprising:
a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level;
a plurality of first test wires each positioned within the first metal level and extending in a first direction, wherein each of the plurality of first test wires is electrically insulated from the monitor chain and positioned laterally between two of the plurality of metal wires; and
a plurality of second test wires each positioned within the second metal level and extending in a second direction, wherein each of the plurality of second test wires is electrically insulated from the monitor chain and positioned laterally between two of the plurality of metal wires, and wherein the first direction is different from the second direction.

18. The IC test structure of claim 17 , further comprising:
a first spine wire positioned within the first metal level and electrically connected to the plurality of first test wires, wherein the first spine wire extends in the second direction;
a second spine wire positioned within the second metal level and electrically connected to the plurality of second test wires, wherein the second spine wire extends in the first direction.

19. The IC test structure of claim 17 , further comprising a plurality of interconnect vias each electrically coupled to one of the first test wire and the second test wire, and extending from the first metal level to the second metal level.

20. The IC test structure of claim 17 , wherein each of the plurality of first test wires and the plurality of second test wires are free of vias electrically connected thereto.

Assignees

• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Kim Andrew T
• Christiansen Cathryn J
• Wang Ping-Chuan

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/2886

  Features relating to contacting the IC under test, e.g. probe heads; chucks (G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06) · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic