Puncture-aware low density parity check (LDPC) decoding

Patent metadata

Field	Value
Publication number	US-9432052-B2
Application number	US-201414501719-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Sep 18, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A communication device or device includes a processor that generates and interprets signals that are transmitted and received via a communication interface. The processor receives an LDPC coded signal, via the communication interface, that is generated by puncturing at least one parity bit from another LDPC coded signal that is generated based on an LDPC code characterized by a first LDPC matrix. The processor operates on the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix. The number of columns and rows excluded from the first LDPC matrix is based on the number of bits punctured from the other LDPC coded signal to generate the LDPC coded signal. The processor then decodes the LDPC coded signal using the second LDPC matrix to make estimates of information bits encoded within the LDPC coded signal.

First claim

What is claimed is:

1. A communication device comprising:
a communication interface; and
a processor, the processor and communication interface configured to:
receive a low density parity check (LDPC) coded signal, wherein the LDPC coded signal is generated from an other LDPC coded signal that has had at least one parity bit punctured there from, wherein the other LDPC coded signal is generated based on an LDPC code that is characterized by a first LDPC matrix;
process the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix based on a number of bits of the at least one parity bit punctured from the other LDPC coded signal to generate the LDPC coded signal; and
decode the LDPC coded signal using the second LDPC matrix to make a plurality of estimates of a plurality of information bits encoded within the LDPC coded signal.

2. The communication device of claim 1 , wherein the first LDPC matrix includes a plurality of sub-matrices arranged in a left hand side matrix and a right hand side matrix, wherein the right hand side matrix is lower triangular and includes a first plurality of all-zero-valued sub-matrices located above and to the right of a main diagonal of the right hand side matrix, wherein a first plurality of CSI (Cyclic Shifted Identity) sub-matrices are located on the main diagonal of the right hand side matrix, and wherein a second plurality of CSI sub-matrices and a second plurality of all-zero-valued sub-matrices are located below and left of the main diagonal of the right hand side matrix.

3. The communication device of claim 1 , wherein the processor and communication interface are further configured to:
process the first LDPC matrix to generate the second LDPC matrix by excluding a plurality of columns and a plurality of rows from the first LDPC matrix based on the number of bits of the at least one parity bit punctured from the other LDPC coded signal to generate the LDPC coded signal, wherein a number of columns within the plurality of columns is same as a number of rows within the plurality of rows.

4. The communication device of claim 1 , wherein:
the second LDPC matrix includes an upper left-hand portion of the first LDPC matrix;
a first difference between a first number of columns of the first LDPC matrix and a second number of columns of the second LDPC matrix is same as the number of bits of the at least one parity bit punctured from the other LDPC coded signal to generate the LDPC coded signal; and
a second difference between a first number of rows of the first LDPC matrix and a second number of rows of the second LDPC matrix is same as the number of bits of the at least one parity bit punctured from the other LDPC coded signal to generate the LDPC coded signal.

5. The communication device of claim 1 , wherein the processor and communication interface are further configured to:
receive a first other LDPC coded signal, wherein the first other LDPC coded signal is generated from a second other LDPC coded signal that has had an other at least one parity bit punctured there from, wherein the second other LDPC coded signal is generated based on the LDPC code that is characterized by the first LDPC matrix;
process the first LDPC matrix to generate a third LDPC matrix by excluding an other at least one column and an other at least one row from the first LDPC matrix based on an other number of bits of the other at least one parity bit punctured from the second other LDPC coded signal to generate the first other LDPC coded signal; and
decode the first LDPC coded signal using the third LDPC matrix to make an other plurality of estimates of an other plurality of information bits encoded within the first other LDPC coded signal.

6. The communication device of claim 1 , wherein the processor and communication interface are further configured to:
receive a first other LDPC coded signal, wherein the first other LDPC coded signal is generated from a second other LDPC coded signal that has had an other at least one parity bit punctured there from, wherein the second other LDPC coded signal is generated based on the LDPC code that is characterized by a third LDPC matrix;
process the third LDPC matrix to generate a fourth LDPC matrix by excluding at least one column and at least one row from the third LDPC matrix based on an other number of bits of the other at least one parity bit punctured from the second other LDPC coded signal to generate the first other LDPC coded signal; and
decode the first LDPC coded signal using the fourth LDPC matrix to make an other plurality of estimates of an other plurality of information bits encoded within the first other LDPC coded signal.

7. The communication device of claim 1 , wherein the LDPC code is a non-binary LDPC code.

8. The communication device of claim 1 further comprising:
the processor and the communication interface configured to support communications within at least one of a satellite communication system, a wireless communication system, a wired communication system, a fiber-optic communication system, or a mobile communication system.

9. A communication device comprising:
a communication interface; and
a processor, the processor and communication interface configured to:
receive a low density parity check (LDPC) coded signal, wherein the LDPC coded signal is generated from an other LDPC coded signal that has had at least one parity bit punctured there from, wherein the other LDPC coded signal is generated based on an LDPC code that is characterized by a first LDPC matrix, wherein:
the first LDPC matrix includes a plurality of sub-matrices arranged in a left hand side matrix and a right hand side matrix;
the right hand side matrix is lower triangular and includes a first plurality of all-zero-valued sub-matrices located above and to the right of a main diagonal of the right hand side matrix;
a first plurality of CSI (Cyclic Shifted Identity) sub-matrices are located on the main diagonal of the right hand side matrix; and
a second plurality of CSI sub-matrices and a second plurality of all-zero-valued sub-matrices are located below and left of the main diagonal of the right hand side matrix;

process the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix based on a number of bits of the at least one parity bit punctured from the other LDPC coded signal to generate the LDPC coded signal, wherein the second LDPC matrix includes an upper left-hand portion of the first LDPC matrix; and
decode the LDPC coded signal using the second LDPC matrix to make a plurality of estimates of a plurality of information bits encoded within the LDPC coded signal.

10. The communication device of claim 9 , wherein the processor and communication interface are further configured to:
process the first LDPC matrix to generate the second LDPC matrix by excluding a plurality of columns and a plurality of rows from the first LDPC matrix based on the number of bits of the at least one parity bit punctured from the other LDPC coded signal to generate the LDPC coded signal, wherein a number of columns within the plurality of columns is same as a number of rows within the plurality of rows.

11. The communication device of claim 9 , wherein:
a first difference between a first number of columns of the first LDPC matrix and a second number of columns of the second LDPC matrix is same as the number of bits of the at least one parity bit punctured from the other LDPC coded signal to generate the LDPC coded signal; and
a second difference between a first number of rows of the first LDPC matr

Assignees

• Broadcom Corp

Inventors

• Korb Matthias
• Blanksby Andrew John

Classifications

• H03M13/116

  Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices · CPC title

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/618

  Shortening and extension of codes · CPC title

• H03M13/1185

  wherein the parity-check matrix comprises a part with a double-diagonal · CPC title

• H03M13/1165

  QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2] · CPC title