Power generating circuit, frequency generating circuit and frequency control system

Patent metadata

Field	Value
Publication number	US-9432027-B1
Application number	US-201514822042-A
Country	US
Kind code	B1
Filing date	Aug 10, 2015
Priority date	Mar 19, 2015
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A frequency control system includes a power generating circuit and a frequency generating circuit. The power generating circuit includes an up transistor circuit, a down transistor circuit and a capacitor for generating a stable voltage. The frequency generating circuit includes a digital-to-analog converter (DAC), a current source/sink circuit, a voltage-controlled oscillator (VCO) and a digital controller. The DAC receives the stable voltage as a power, the current source/sink circuit receives an analog signal from the DAC, the VCO receives a control voltage from the current source/sink circuit, and the digital controller receives a frequency signal from the VCO and a reference signal, according to which a digital signal is generated and fed to the DAC.

First claim

What is claimed is:

1. A frequency control system, comprising:
a power generating circuit including an up transistor circuit, a down transistor circuit and a capacitor, the up transistor circuit and the down transistor circuit being connected in series and having a node situated therebetween, the capacitor being electrically coupled between the node and ground, a stable voltage being generated at the node; and
a frequency generating circuit including:
a digital-to-analog converter (DAC) receiving the stable voltage as a power, the DAC outputting an analog signal;
a current source/sink circuit receiving the analog signal and outputting a control voltage;
a voltage-controlled oscillator (VCO) receiving the control voltage and according generating a frequency signal; and
a digital controller receiving the frequency signal and a reference signal, according to which a digital signal is generated and fed to an input end of the DAC.

2. The frequency control system of claim 1 , wherein the up transistor circuit comprises at least one transistor, and the down transistor circuit comprises at least one transistor.

3. The frequency control system of claim 2 , wherein said at least one transistor of the up transistor circuit or the down transistor circuit is diode-connected or operates at a cut-off region.

4. The frequency control system of claim 1 , further comprising a first unity-gain buffer disposed between the stable voltage and the DAC, the first unity-gain buffer receiving the stable voltage, which is outputted to the DAC as the power.

5. The frequency control system of claim 4 , wherein the first unity-gain buffer comprises an operational amplifier having an output end connected to an inverting input end, and having a non-inverting input end to receive the stable voltage.

6. The frequency control system of claim 1 , wherein the current source/sink circuit comprises a second unity-gain buffer.

7. The frequency control system of claim 6 , wherein the second unity-gain buffer comprises an operational amplifier having an output end connected to an inverting input end, and having a non-inverting input end to receive the analog signal.

8. The frequency control system of claim 1 , wherein the VCO comprises a ring oscillator.

9. The frequency control system of claim 8 , wherein the VCO comprises a plurality of inverters, which are connected in parallel, each inverter being electrically coupled between the control voltage and ground.

10. The frequency control system of claim 9 , wherein the VCO comprises odd number of inverters.

11. The frequency control system of claim 1 , wherein the digital controller performs the following steps:
inputting the reference signal and the frequency signal;
counting the frequency signal during a period of the reference signal to result in an amount, which is compared with a predetermined number;
maintaining the digital signal if the amount is equal to the predetermined number; and
adjusting the digital signal if the amount is not equal to the predetermined number.

12. The frequency control system of claim 11 , wherein the digital signal is increased if the amount is less than the predetermined number; and the digital signal is decreased if the amount is greater than the predetermined number.

13. A power generating circuit, comprising:
an up transistor circuit;
a down transistor circuit, the up transistor circuit and the down transistor circuit being connected in series and having a node situated therebetween; and
a capacitor being electrically coupled between the node and ground, a stable voltage being generated at the node.

14. The power generating circuit of claim 13 , wherein the stable voltage is fed to a digital-to-analog converter (DAC) as a power.

15. The power generating circuit of claim 13 , wherein the up transistor circuit comprises at least one transistor, and the down transistor circuit comprises at least one transistor.

16. The power generating circuit of claim 15 , wherein said at least one transistor of the up transistor circuit or the down transistor circuit is diode-connected or operates at a cut-off region.

17. A frequency generating circuit, comprising:
a digital-to-analog converter (DAC) receiving a stable voltage as a power, the DAC outputting an analog signal;
a current source/sink circuit receiving the analog signal and outputting a control voltage;
a voltage-controlled oscillator (VCO) receiving the control voltage and according generating a frequency signal; and
a digital controller receiving the frequency signal and a reference signal, according to which a digital signal is generated and fed to an input end of the DAC.

18. The frequency generating circuit of claim 17 , further comprising a first unity-gain buffer disposed between the stable voltage and the DAC, the first unity-gain buffer receiving the stable voltage, which is outputted to the DAC as the power.

19. The frequency generating circuit of claim 18 , wherein the first unity-gain buffer comprises an operational amplifier having an output end connected to an inverting input end, and having a non-inverting input end to receive the stable voltage.

20. The frequency generating circuit of claim 17 , wherein the current source/sink circuit comprises a second unity-gain buffer.

21. The frequency generating circuit of claim 20 , wherein the second unity-gain buffer comprises an operational amplifier having an output end connected to an inverting input end, and having a non-inverting input end to receive the analog signal.

22. The frequency generating circuit of claim 17 , wherein the VCO comprises a ring oscillator.

23. The frequency generating circuit of claim 22 , wherein the VCO comprises a plurality of inverters, which are connected in parallel, each inverter being electrically coupled between the control voltage and ground.

24. The frequency generating circuit of claim 23 , wherein the VCO comprises odd number of inverters.

25. The frequency generating circuit of claim 17 , wherein the digital controller performs the following steps:
inputting the reference signal and the frequency signal;
counting the frequency signal during a period of the reference signal to result in an amount, which is compared with a predetermined number;
maintaining the digital signal if the amount is equal to the predetermined number; and
adjusting the digital signal if the amount is not equal to the predetermined number.

26. The frequency generating circuit of claim 25 , wherein the digital signal is increased if the amount is less than the predetermined number; and the digital signal is decreased if the amount is greater than the predetermined number.

Assignees

• Egalax_Empia Tech Inc

Inventors

• Lin Po-Chuan

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0896

  the current generators being controlled by differential up-down pulses · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title