Semiconductor package with a bridge interposer

Patent metadata

Field	Value
Publication number	US-9431371-B2
Application number	US-201514701388-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	Dec 28, 2011
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

First claim

The invention claimed is:

1. A semiconductor package comprising:
a bridge interposer comprising an interposer dielectric with an intra-interposer routing trace formed in the interposer dielectric;
a first active die having a first portion situated under said bridge interposer, and a second portion not situated under said bridge interposer;
a second active die having a first portion situated under said bridge interposer, and a second portion not situated under said bridge interposer;
said first active die and said second active die configured to communicate with each other through said bridge interposer; and
a package substrate situated under said first active die and said second active die, said first active die and said second active die configured to communicate electrical signals to said package substrate utilizing bond wires,
wherein the intra-interposer routing trace has a first end for coupling to the first active die and a second end for coupling to the second active die, the entire length of the intra-interposer routing trace between the first end and the second end being within the interposer dielectric.

2. The semiconductor package of claim 1 , wherein said first active die is configured to communicate direct current (DC) signals to said second active die through said bridge interposer.

3. The semiconductor package of claim 1 , wherein the bridge interposer comprises alternating current (AC) signal pads, and wherein said first active die is configured to communicate AC signals to said second active die by utilizing the AC signal pads in said bridge interposer.

4. The semiconductor package of claim 1 , wherein the bridge interposer further comprises a first signal pad and a second signal pad formed therein, and wherein the intra-interposer routing trace couples to the first signal pad and the second signal pad.

5. The semiconductor package of claim 1 , wherein the bridge interposer comprises a first signal pad and a second signal pad formed in the interposer dielectric, and wherein the first end of the intra-interposer routing trace couples to the first signal pad and the second end of the intra-interposer routing trace couples to the second signal pad.

6. The semiconductor package of claim 1 , wherein:
the bridge interposer comprises a second intra-interposer routing trace formed in the interposer dielectric,
the second intra-interposer routing trace has a first end for coupling to the first active die and a second end for coupling to the second active die, and
the entire length of the second intra-interposer routing trace being within the interposer dielectric.

7. A semiconductor package comprising:
a bridge interposer having a first surface including alternating current (AC) signal pads;
a first active die having a first portion and a second portion, the first portion of the first active die facing said first surface of said bridge interposer; and
a second active die having a first portion and a second portion, the first portion of the second active die facing said first surface of said bridge interposer, the second portion of the first active die and the second portion of the second active die including solder balls mounted on a package substrate,
wherein:
said first active die and said second active die are configured to communicate AC chip-to-chip signals utilizing said AC signal pads of said bridge interposer,
the first active die and the second active die are configured to communicate electrical signals to the package substrate utilizing the solder balls, and
the solder balls are coupled to the second portion of the first active die and the second portion of the second active die by respective conductive pillars.

8. The semiconductor package of claim 7 , wherein said first active die and said second active die are configured to communicate direct (DC) chip-to-chip signals through said bridge interposer.

9. The semiconductor package of claim 7 , wherein said bridge interposer comprises intra-interposer routing traces formed therein.

10. The semiconductor package of claim 7 , wherein said bridge interposer comprises an interposer dielectric with an intra-interposer routing trace formed in the interposer dielectric.

11. The semiconductor package of claim 10 , wherein the intra-interposer routing trace has a first end for coupling to the first active die and a second end for coupling to the second active die, the entire length of the intra-interposer routing trace between the first end and the second end being within the interposer dielectric.

12. The semiconductor package of claim 7 , wherein said first active die and said second active die are configured to communicate electrical signals to said package substrate utilizing said solder balls and without utilizing through-semiconductor vias (TSVs).

13. The semiconductor package of claim 7 , further comprising a passivation layer formed on said second portion of said first active die and said second portion of said second active die between said respective conductive pillars.

14. A semiconductor package comprising:
a first die comprising a structure to receive or receiving a bond wire;
a second die; and
a bridge interposer situated over at least a portion of each of the first die and the second die, wherein the bridge interposer comprises an interposer dielectric with at least one routing trace formed in the interposer dielectric, the second die configured to communicate chip-to-chip signals with the first die through the at least one routing trace,
wherein:
a portion of the first die is not situated under the bridge interposer,
the at least one routing trace has a first end for coupling to the first die and a second end for coupling to the second die, and
the entire length of the at least one routing trace between the first end and the second end being within the interposer dielectric.

15. The semiconductor package of claim 14 , further comprising a package substrate having a structure to receive or receiving the bond wire.

16. The semiconductor package of claim 14 , wherein the bridge interposer is devoid of conductive through-vias.

17. The semiconductor package of claim 14 , wherein:
the bridge interposer comprises a first signal pad and a second signal pad formed therein, and
the first signal pad is connected to the second signal pad by the at least one routing trace.

18. The semiconductor package of claim 17 , wherein:
the first die comprises a signal pad,
the second die comprises a signal pad, and
the second die is configured to communicate chip-to-chip signals with the first die through the at least one routing trace, the signal pad of the first die, the signal pad of the second die, the first signal pad, and the second signal pad.

19. The semiconductor package of claim 18 , further comprising an adhesion layer between the signal pad of the first die and the first signal pad.

20. The semiconductor package of claim 14 , wherein each of the at least one routing trace consists of one or more conductive materials.

21. The semiconductor package of claim 14 , wherein the first die has a structure to receive the bond wire or receiving at the portion of the first die that is not situated under the bridge interposer.

Assignees

• Broadcom Corp

Inventors

• Karikalan Sampath K
• Zhao Sam Ziqun
• Hu Kevin Kunzhong
• Khan Rezaur Rahman
• Vorenkamp Pieter
• Chen Xiangdong

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title