Compliant dielectric layer for semiconductor device

Patent metadata

Field	Value
Publication number	US-9431370-B2
Application number	US-201414147237-A
Country	US
Kind code	B2
Filing date	Jan 3, 2014
Priority date	Dec 19, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
a semiconductor material body having opposing first and second surfaces, and including a first electrically conductive feature at the first surface;
a compliant dielectric material layer having opposing first and second surfaces, the first surface of the compliant dielectric material layer on the second surface of the semiconductor material body, the compliant dielectric material layer having a deformability that is greater than a deformability of the semiconductor material body;
a second electrically conductive feature formed on the second surface of the compliant dielectric material layer;
an electrically conductive via formed through the semiconductor material body and the compliant dielectric material layer that electrically couples the first electrically conductive feature to the second electrically conductive feature;
a passivation layer between the compliant dielectric material layer and the semiconductor material body, and between the compliant dielectric material layer and the electrically conductive via, the electrically conductive via within the semiconductor material body lacking the passivation layer; and
an interconnect member coupled to the second surface of the compliant dielectric material layer in electrical contact with the second electrically conductive feature.

2. The IC package of claim wherein the semiconductor material body includes an active integrated circuit.

3. The IC package of claim 1 , wherein the semiconductor material body is configured as an interposer for the IC package, and the IC package further comprises:
an IC die mounted to the first surface of the interposer.

4. The IC package of claim 1 ,
wherein the electrically conductive via is not coated by the passivation layer at the second surface of the compliant dielectric material layer.

5. The IC package of claim I, wherein the compliant dielectric material layer comprises:
a plurality of compliant dielectric material sub-layers.

6. The IC package of claim 5 , wherein at least two of the compliant dielectric material sub-layers comprise different dielectric materials front each other.

7. The IC package of claim 1 , wherein the IC package is configured to be attached to a circuit board using the interconnect member, and
wherein the compliant dielectric material layer has a coefficient of thermal expansion that is approximately the same as the circuit board.

8. An integrated circuit (IC) package, comprising:
an interposer having opposing first and second surfaces, that comprises:
a semiconductor material body having opposing first and second surfaces;
a compliant dielectric material layer having opposing first and second surfaces, the first surface of the compliant dielectric material layer on the second surface of the semiconductor material body, the compliant dielectric material layer having a deformability that is greater than a deformability of the semiconductor material body, the compliant dielectric material layer comprising a plurality of compliant dielectric material sub-layers;
a first electrically conductive via and a second electrically conductive via each formed through the semiconductor material body and the compliant dielectric material layer; and
at least one IC die mounted to the first surface of the interposer.

9. The IC package of claim 8 , further comprising:
a first electrically conductive feature formed on the first surface of the semiconductor material body;
a second electrically conductive feature formed on the first surface of the semiconductor material body;
a third electrically conductive feature formed on the second surface of the compliant dielectric material layer;
a fourth electrically conductive feature formed on the second surface of the compliant dielectric material layer;
a first interconnect member coupled to the first surface of the compliant dielectric material layer and in electrical contact with the first electrically conductive feature;
a second interconnect member coupled to the first surface of the compliant dielectric material layer and in electrical contact with the second electrically conductive feature;
a third interconnect member coupled to the second surface of the compliant dielectric material layer and in electrical contact with the third electrically conductive feature; and
a fourth interconnect member coupled to the second surface of the compliant dielectric material layer and in electrical contact with the fourth electrically conductive feature.

10. The IC package of claim 9 , wherein the first electrically conductive via electrically couples the first electrically conductive feature to the third electrically conductive feature, and
wherein the second electrically conductive via electrically couples the second electrically conductive feature to the fourth electrically conductive feature.

11. The IC package of claim 10 , wherein a first IC die is coupled to the first interconnect member and a second IC die is coupled to the second interconnect member, and
wherein the third interconnect member and the fourth interconnect member are each coupled to a circuit board.

12. The IC package of claim 11 , wherein the compliant dielectric material has a coefficient of thermal expansion property that is approximately equal to a coefficient of thermal expansion property of the circuit board.

13. The IC package of claim 12 , wherein the first surface of the interposer has an area of at least 625 mm 2 .

14. A semiconductor device, comprising:
a semiconductor material body having opposing first and second surfaces;
a compliant dielectric material layer having opposing first and second surfaces, the first surface of the compliant dielectric material layer on the second surface of the semiconductor material body, the compliant dielectric material layer having a deformability that is greater than a deformability of the semiconductor material body the compliant dielectric material layer comprising a plurality of compliant dielectric material sub-layers;
an electrically conductive via passing through the semiconductor material body and the compliant dielectric material layer and in electrical contact with a metal layer on the first surface of the semiconductor material body, a first sub-layer of the plurality of compliant dielectric material sub-layers being between the electrically conductive via and a second sub-layer of the plurality of compliant dielectric material sub-layers; and
an interconnect member coupled to the second surface of the compliant dielectric material layer in electrical contact with the electrically conductive via.

15. The semiconductor device of claim 14 , wherein the semiconductor material body includes an active integrated circuit (IC).

16. The semiconductor device of claim 15 , wherein the semiconductor material body is configured as an interposer for an IC package, and the first surface of the interposer comprises a plurality of electrically conductive features configured to mount an IC die.

17. The semiconductor device of claim 14 , wherein the semiconductor material body is configured as an interposer for an integrated circuit (IC) package, and the first surface of the interposer comprises a plurality of electrically conductive features configured to mount an IC die.

18. The semiconductor device of claim 14 , further comprising:
a passivation layer between the compliant dielectric material layer and the semiconductor material body, and between the compliant dielectric material layer and the electrically con

Assignees

• Broadcom Corp

Inventors

• Khan Rezaur Rahman
• Zhao Sam Ziqun

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title