Memory devices and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9431107-B2
Application number	US-201213715641-A
Country	US
Kind code	B2
Filing date	Dec 14, 2012
Priority date	Dec 14, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.

First claim

What is claimed is:

1. A memory device, comprising:
a transistor including a gate disposed over a surface of a workpiece and a source region and a drain region disposed in the workpiece proximate the gate, the source region and the drain region each extending from the surface of the workpiece into the workpiece; and
an erase gate including a tip portion that extends in a recess in the workpiece, the recess extending from the surface of the workpiece into the workpiece, wherein the erase gate directly contacts the gate of the transistor; and
a coupling gate over the workpiece, the coupling gate directly contacting the gate of the transistor.

2. The memory device according to claim 1 , wherein the gate of the transistor is integrally connected to the erase gate.

3. The memory device according to claim 1 , further comprising an insulating material disposed between the tip portion of the erase gate and the workpiece.

4. The memory device according to claim 3 , wherein the insulating material comprises a thickness of about 70 Angstroms or greater.

5. The memory device according to claim 1 , wherein the tip portion of the erase gate extends below a bottom surface of the gate of the transistor by about 50 to 3,000 Angstroms.

6. The memory device according to claim 1 , wherein the gate of the transistor is integrally connected to the coupling gate.

7. A memory device, comprising:
a first capacitor;
a second capacitor coupled in series with the first capacitor; and
a transistor including a gate on a workpiece and source/drain regions disposed in the workpiece, the gate of the transistor being directly connected to a node in series between the first capacitor and the second capacitor, wherein the first capacitor includes a first plate disposed in the workpiece, a first insulating material disposed over the workpiece, and a second plate disposed over the first insulating material, and wherein the first plate is distinct from each of the source/drain regions, wherein the second plate of the first capacitor includes a tip portion that extends in a recess in the workpiece.

8. The memory device according to claim 7 , wherein the transistor is erasable using the first capacitor.

9. The memory device according to claim 8 , wherein the tip portion of the second plate of the first capacitor comprises an erase tip.

10. The memory device according to claim 9 , wherein the transistor is adapted to store a bit of information, and wherein the bit of information is erasable using the erase tip.

11. The memory device according to claim 7 , wherein the transistor is programmable using the second capacitor.

12. The memory device according to claim 7 , wherein the transistor is readable using the second capacitor.

13. A memory device comprising:
a conductive electrode on a workpiece, the conductive electrode extending across a first region of the workpiece, a second region of the workpiece, and a third region of the workpiece;
a first capacitor in the first region of the workpiece, the first capacitor comprising a first electrode in the workpiece and an erase gate electrode, the erase gate electrode being a first portion of the conductive electrode on the workpiece, the conductive electrode extending into a recess in the workpiece in the first region;
a transistor in the second region of the workpiece, the transistor comprising a source/drain region in the workpiece and a gate, the gate being a second portion of the conductive electrode on the workpiece; and
a second capacitor in the third region of the workpiece, the second capacitor comprising a second electrode in the workpiece and a coupling gate electrode, the coupling gate electrode being a third portion of the conductive electrode on the workpiece.

14. The memory device of claim 13 , wherein the conductive electrode is a floating conductive electrode.

15. The memory device of claim 13 further comprising a dielectric layer disposed between the conductive electrode and the workpiece.

16. The memory device of claim 13 , wherein the recess has a v-shaped cross section.

17. The memory device of claim 13 , wherein the first electrode comprises a first doped region of the workpiece, and the second electrode comprises a second doped region of the workpiece.

18. The memory device of claim 13 , wherein a cross section of the conductive electrode in a plane parallel to a top surface of the workpiece is an L-shape.

19. The memory device of claim 13 , wherein a cross section of the conductive electrode in a plane parallel to a top surface of the workpiece is a rectangular shape.

20. The memory device of claim 7 , wherein the second capacitor includes a third plate disposed in the workpiece, a second insulating material disposed over the workpiece, and a fourth plate disposed over the second insulating material, and wherein the third plate is distinct from each of the source/drain regions.

21. The memory device of claim 20 , wherein the second plate, the gate, and the fourth plate are each an integral portion of a same conductive feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kalnitsky Alexander
• Tuan Hsiao-Chin
• Tsui Felix Ying-Kit
• Lu Hau-Yan

Classifications

• G11C16/0441 Primary

  comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/0411 Primary

  of FETs having floating gates · CPC title