Non-volatile memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9171622-B2
Application number	US-201313843846-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Dec 21, 2012
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

This technology provides a non-volatile memory device and a method of manufacturing the same, which may prevent an over-erase phenomenon and also increase the degree of integration, In an aspect, the non-volatile memory device includes a select gate formed over a substrate, a plurality of floating gates laterally formed with respect to the select gate and spaced apart from each other, to be independently programmable, and a plurality of junctions formed in the substrate and arranged to be controllable by the respective floating gates.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a select gate formed over a substrate;
a plurality of floating gates laterally formed with respect to the select gate and spaced apart from each other, to be independently programmable, wherein each of the plurality of floating gates is laterally coupled to the select gate; and
a plurality of junctions formed in the substrate and arranged to be controllable by the respective floating gates,
wherein a floating gate adjacent to any one of the plurality of junctions, from among the plurality of floating gates, is programmed in response to only a bias supplied to the select gate and a bias supplied to the any one junction.

2. The non-volatile memory device of claim 1 , further comprising charge block layers formed between the select gate and the plurality of floating gates.

3. The non-volatile memory device of claim 1 , further comprising:
a second well formed in the substrate; and
a first well formed in the second well and having a conduction type complementary to the second well,
wherein the plurality of floating gates overlaps with the second well and the first well.

4. The non-volatile memory device of claim 3 , wherein the plurality of floating gates is erased in response to a bias supplied to the second well, or a bias supplied to the first well, or a bias supplied to the second well and a bias supplied to the first well.

5. The non-volatile memory device of claim 1 , wherein the plurality of floating gates has a spacer type.

6. The non-volatile memory device of claim 1 , wherein the plurality of floating gates is simultaneously coupled in response to a bias supplied to the select gate.

7. A non-volatile memory device, comprising:
a select gate formed over a substrate;
a first floating gate formed on one of sidewalls of the select gate;
a second floating gate formed on the other of the sidewalls of the select gate;
a first junction formed in the substrate under the first floating gate; and
a second junction formed in the substrate under the second floating gate,
wherein the first floating gate and the second floating gate are independently programmable,
wherein each of the first floating gate and the second floating gate is coupled to the select gate,
wherein the first floating gate is programmed in response to only a bias supplied to the select gate and a bias supplied to the first junction, and
wherein the second floating gate is programmed in response to only a bias supplied to the select gate and a bias supplied to the second junction.

8. The non-volatile memory device of claim 7 , further comprising charge block layers formed between the select gate and the first floating gate and between the select gate and the second floating gate, respectively.

9. The non-volatile memory device of claim 7 , further comprising:
a second well formed in the substrate; and
a first well formed in the second well and having a conduction type complementary to the second well,
wherein the first floating gate and the second floating gate overlap with the second well and the first well, respectively.

10. The non-volatile memory device of claim 9 , wherein the first floating gate and the second floating gate are erased in response to a bias supplied to the second well, or a bias supplied to the first well, or both a bias supplied to the second well and a bias supplied to the first well.

11. The non-volatile memory device of claim 7 , wherein the first floating gate and the second floating gate have a spacer type.

12. The non-volatile memory device of claim 7 , wherein the first floating gate and the second floating gate are simultaneously coupled in response to a bias supplied to the select gate.

13. A non-volatile memory device, comprising:
a substrate including a plurality of active regions;
a plurality of word lines crossing the active regions;
a plurality of junctions formed in the active region between the word lines; and
a bit line and a source line connected to the respective junctions on one side and the other side of any one of the word lines,
wherein the word line comprises a select gate crossing the active region and a plurality of floating gates formed on sidewalls of the select gate in such a way as to overlap with the active region and spaced apart from each other in such a way as to be independently programmed,
wherein any one of the plurality of floating gates is programmed in response to only a bias supplied to the bit line and a bias supplied to the select gate, or only a bias supplied to the source line and a bias supplied to the select gate, and
wherein each of the plurality of floating gates is coupled to the select gate.

14. The non-volatile memory device of claim 13 , further comprising charge block layers formed between the select gate and the plurality of floating gates.

15. The non-volatile memory device of claim 13 , further comprising:
a second well formed in the substrate and including the plurality of active regions; and
a plurality of first wells formed in the second well in response to the plurality of active regions.

16. The non-volatile memory device of claim 15 , wherein the plurality of floating gates is erased in response to a bias supplied to the select gate and a bias supplied to the second well, or a bias supplied to the select gate and a bias supplied to the first well, or a bias supplied to the select gate and both a bias supplied to the second well and a bias supplied to the first well.

17. The non-volatile memory device of claim 13 , wherein the plurality of floating gates has a spacer type.

18. The non-volatile memory device of claim 13 , wherein the plurality of floating gate formed on the sidewalls of the select gate is simultaneously coupled in response to a bias supplied to the select gate.

Assignees

• Sk Hynix Inc

Inventors

• Kwon Young-Jun

Classifications

• G11C16/0441 Primary

  comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates · CPC title

• G11C16/3477 Primary

  Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D84/0156

  Manufacturing their doped wells · CPC title

• H10D30/0411 Primary

  of FETs having floating gates · CPC title