Neuromorphic device with excitatory and inhibitory functionalities

Patent metadata

Field	Value
Publication number	US-9431099-B2
Application number	US-201514935658-A
Country	US
Kind code	B2
Filing date	Nov 9, 2015
Priority date	Nov 11, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Provided is a neuromorphic device including first and second lower electrodes formed on a substrate to be electrically separated, first and second lower insulating film stacks formed at least on respective surfaces of the first and second lower electrodes, first, second, and third doped regions formed at left and right sides of the first and second lower electrodes, first and second semiconductor regions formed on the first and second lower insulating film stacks, an upper insulating film stack formed on the first and second semiconductor regions and the first, second, and third doped regions, and an upper electrode formed on the upper insulating film stack. Accordingly, a specified neuromorphic device can be reconfigured to have arbitrarily inhibitory or excitatory functionality by using the first and second lower electrodes and the lower insulating film stacks including charge storage layers formed on the surfaces of the electrodes.

First claim

What is claimed is:

1. A neuromorphic device comprising:
first, second, and third doped regions which are formed with a semiconductor material doped with impurities on a substrate to be electrically separated by a predetermined distance from each other and to be electrically isolated from each other;
a first lower electrode which is disposed between the first doped region and the second doped region to be electrically insulated from the first and second doped regions;
a second lower electrode which is disposed between the second doped region and the third doped region to be electrically insulated from the second and third doped region;
a first lower insulating film stack which is disposed at least on a surface of the first lower electrode;
a second lower insulating film stack which is disposed at least on a surface of the second lower electrode;
a first semiconductor region which is formed on a top surface of the first lower insulating film stack to connect the first doped region and the second doped region;
a second semiconductor region which is formed on a top surface of the second lower insulating film stack to connect the second doped region and the third doped region;
an upper insulating film stack which is formed on top surfaces of the first and second semiconductor regions; and
an upper electrode which is disposed on the upper insulating film stack.

2. The neuromorphic device according to claim 1 , further comprising lower insulating film stacks between the substrate and the first doped region, between the substrate and the second doped region, and between the substrate and the third doped region.

3. The neuromorphic device according to claim 1 , wherein each of the first and second lower insulating film stacks is configured in a structure where a plurality of layers including at least a charge storage layer and an insulating film are stacked.

4. The neuromorphic device according to claim 1 , wherein the upper insulating film stack is configured with a single insulating material or in a stack structure where a plurality of layers including at least a charge storage layer and an insulating film are stacked.

5. The neuromorphic device according to claim 1 , wherein the first and second lower insulating film stacks are configured so that each of the first and second lower insulating film stacks only on top surfaces of the first and second lower electrodes is configured in a stack structure where a plurality of layers including at least a charge storage layer and an insulating film are stacked and each of the first and second lower insulating film stacks on remaining regions is configured with a single insulating film.

6. The neuromorphic device according to claim 1 , wherein each of the first and second lower insulating film stacks and the upper insulating film stack is configured in a stack structure where a plurality of layers including at least a charge storage layer and an insulating film are stacked, and the charge storage layer of each of the first and second lower insulating film stacks and the charge storage layer of the upper insulating film stack are different from each other in terms of a charge storage time interval.

7. The neuromorphic device according to claim 1 , wherein a doped region formed to be doped with impurities of which type is different from that of the first, second, and third doped regions is further disposed on one side surface of the first and second semiconductor regions.

8. The neuromorphic device according to claim 1 , wherein the first and second semiconductor regions are doped with impurities of which type is opposite to that of the first, second, and third doped regions.

9. The neuromorphic device according to claim 4 , wherein in the case where the upper gate insulating film includes the charge storage layer and the insulating film, a program or erase operation is performed by injecting carriers (electrons or holes) from the upper electrode or the first and second semiconductor regions.

10. The neuromorphic device according to claim 6 , wherein in the case where each of the first and second lower insulating film stacks and the upper insulating film stack is configured in the stack structure where a plurality of the layers including at least the charge storage layer and the insulating film are stacked, the charge storage layer is configured with an insulating film including traps, an insulating film including nano particles, or an electrode.

11. The neuromorphic device according to claim 1 ,
wherein each of the first and second lower insulating film stacks includes a charge storage layer, and
wherein positive or negative charges are stored in the charge storage layer so that threshold values of FETs formed in the first and second lower insulating film stacks are controlled.

12. A neuromorphic device array comprising a plurality of the neuromorphic devices according to claim 1 ,
wherein the neuromorphic devices share first and second lower electrodes and first, second, and third doped regions, and the neuromorphic devices are connected to each other through a plurality of upper electrodes which are electrically separated from each other.

13. The neuromorphic device array according to claim 12 ,
wherein first and second semiconductor regions are shared between the adjacent neuromorphic devices in the array configured with a plurality of the neuromorphic devices, and
wherein voltages of the first and second semiconductor regions and a voltage of the second doped region are controlled by using a first electrode which is electrically in contact with the first and second semiconductor regions shared between the adjacent neuromorphic devices and the second doped region.

14. The neuromorphic device array according to claim 12 ,
wherein first and second semiconductor regions are shared between the adjacent neuromorphic devices in the array configured with a plurality of the neuromorphic devices, and
wherein voltages of the first and second semiconductor regions are controlled by using a first electrode which is electrically in contact with the first and second semiconductor regions shared between the adjacent neuromorphic devices.

15. The neuromorphic device array according to claim 12 ,
wherein side surfaces of the first and second semiconductor regions are exposed between the adjacent neuromorphic devices in the array configured with a plurality of the neuromorphic devices, and
wherein voltages of the first and second semiconductor regions and a voltage of the second doped region are controlled by using a first electrode which is electrically in contact with the first and second semiconductor regions of which the side surfaces are exposed between the adjacent neuromorphic devices and the second doped region.

16. The neuromorphic device array according to claim 12 ,
wherein the first and second semiconductor regions are shared between the adjacent neuromorphic devices in the array configured with a plurality of the neuromorphic devices,
wherein voltages of the first and second semiconductor regions and a voltage of the second doped region are controlled by using a first electrode which is electrically in contact with the first and second semiconductor regions shared between the adjacent neuromorphic devices and the second doped region, and
wherein resistance is decreased by using second and third electrodes which are electrically separated from the first and third doped regions shared between the adjacent neuromorphic devices.

17. The neuromorphic device array according to claim 16 , wherein the first, second, and third electr

Assignees

• Snu R&Db Foundation

Inventors

• Lee Jong-Ho
• Kim Chul-Heung
• Woo Sung-Yun

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title