Coalescing memory transactions

US9430276B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9430276-B2
Application numberUS-201514739049-A
CountryUS
Kind codeB2
Filing dateJun 15, 2015
Priority dateDec 12, 2013
Publication dateAug 30, 2016
Grant dateAug 30, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A transactional memory system coalesces two outermost transactions in a transactional memory environment. A processor of the transactional memory system executes a first transaction begin instruction of a first outermost transaction and processes the first transaction. Based on encountering a first transaction end instruction of the first outermost transaction, the processor determines whether the first transaction is to-be coalesced with a second outermost transaction.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for coalescing two outermost transactions in a transactional memory environment, the method comprising: executing, by a processor, a first transaction begin instruction of a first outermost transaction in which a first nested transaction is nested; based on executing the first transaction begin instruction, processing, by the processor, the first outermost transaction; based on encountering a first transaction end instruction of the first outermost transaction during processing of the first outermost transaction, determining, by the processor, whether the first outermost transaction is to-be coalesced with a second outermost transaction in which a second nested transaction is nested; and based on the determining indicating that the first outermost transaction is to-be coalesced with the second outermost transaction, coalescing, by the processor, the first outermost transaction with the second outermost transaction. 2. The method of claim 1 , wherein coalescing, by the processor, the first outermost transaction with the second outermost transaction includes: prior to processing the second outermost transaction, suspending, by the processor, a first store data to memory operation of the first outermost transaction. 3. The method of claim 1 , wherein coalescing, by the processor, the first outermost transaction with the second outermost transaction includes: based on encountering a second transaction begin instruction of the second outermost transaction, processing, by the processor, the second outermost transaction. 4. The method of claim 1 , wherein coalescing, by the processor, the first outermost transaction with the second outermost transaction includes: based on encountering a second transaction end instruction of the second outermost transaction, committing, by the processor, a second store data to memory operation for both of the first outermost transaction and second outermost transaction, wherein the first outermost transaction and second outermost transaction are coalesced. 5. The method of claim 1 , the method further comprising: identifying, by the processor, one or more instructions that follow the first outermost transaction and precede the second outermost transaction; determining, by the processor, whether the one or more instructions can be processed as part of the coalesced transactions; based on the determining indicating that the one or more instructions can be processed as part of the coalesced transactions, executing, by the processor, the one or more instructions following the first outermost transaction as part of the coalesced first outermost transaction and second outermost transaction; and committing, by the processor, a fifth store data to memory operation for the one or more instructions as part of committing the second store data to memory operation. 6. The method of claim 5 , wherein determining whether the one or more instructions can be processed as part of the first outermost transaction is based on at least one of: i) a time period required to process the one or more instructions, ii) a quantity of resources required to process the one or more instructions, and iii) a category to which the one or more instructions belong. 7. The method of claim 1 , the method further comprising: adding, by the processor, one or more markers to a memory footprint of the first outermost transaction and the second outermost transaction to indicate respective regions of memory that are used for the processing of the first outermost transaction and the second outermost transaction, wherein the memory footprint includes memory addresses that are read from and written to during the processing of the first outermost transaction and the second outermost transaction, and wherein the one or more markers are used for one or both of i) to rollback the coalesced transaction in the case of an abort, and ii) to control coalescing of outermost transactions. 8. The method of claim 1 , wherein the determination whether the first outermost transaction is to-be coalesced with a second outermost transaction is based on at least one of i) a number of instructions between the first outermost transaction and the second outermost transaction, ii) a time period required to process the first outermost transaction and second outermost transaction, iii) a quantity of resources required to process the first outermost transaction and second outermost transaction, iv) a maximum number of transactions that can be coalesced, and v) a history of coalescing outmost transactions that lead to an abort status. 9. A computer program product for coalescing two outermost transactions in a transactional memory environment, the computer program product comprising: one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising: program instructions to execute a first transaction begin instruction of a first outermost transaction in which a first nested transaction is nested; program instructions to process the first outermost transaction based on executing the first transaction begin instruction; program instructions to respond to encountering a first transaction end instruction of the first outermost transaction during processing of the first outermost transaction, by determining whether the first outermost transaction is to-be coalesced with a second outermost transaction in which a second nested transaction is nested; and program instructions to respond to a determination that the first outermost transaction is to-be coalesced with the second outermost transaction, by executing program instructions to coalesce the first outermost transaction with the second outermost transaction. 10. The computer program product of claim 9 , wherein the program instructions coalesce the first outermost transaction with the second outermost transaction include: program instructions to suspend a first store data to memory operation of the first outermost transaction prior to processing the second outermost transaction. 11. The computer program product of claim 9 , wherein the program instructions coalesce the first outermost transaction with the second outermost transaction include: program instructions to based on encountering a second transaction begin instruction of the second outermost transaction, processing, by the processor, the second outermost transaction. 12. The computer program product of claim 9 , wherein the program instructions to coalesce the first outermost transaction with the second outermost transaction include: program instructions to respond to encountering a second transaction end instruction of the second outermost transaction, by committing a second store data to memory operation for both of the first outermost transaction and second outermost transaction, wherein the first outermost transaction and second outermost transaction are coalesced. 13. The computer program product of claim 9 , the program instructions further comprising: program instructions to identify one or more instructions that follow the first outermost transaction and precede the second outermost transaction; program instructions to determine whether the one or more instructions can be processed as part of the coalesced transactions; program instructions to respond to a determination that the one or more instructions can be processed as part of the coalesced transactions, by executing the one or more instructions following the first outermost transaction as part of the coalesced first outermost transaction and second outermost transaction; and program in

Assignees

Inventors

Classifications

  • G06F9/467Primary

    Transactional memory (G06F9/528 takes precedence) · CPC title

  • Access to shared memory · CPC title

  • Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

  • Mutual exclusion algorithms · CPC title

  • in relation to throughput · CPC title

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What does patent US9430276B2 cover?
A transactional memory system coalesces two outermost transactions in a transactional memory environment. A processor of the transactional memory system executes a first transaction begin instruction of a first outermost transaction and processes the first transaction. Based on encountering a first transaction end instruction of the first outermost transaction, the processor determines whether …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F9/467. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 30 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).