Communication unit and sliced radio frequency module therefor

Patent metadata

Field	Value
Publication number	US-9425949-B2
Application number	US-201414274759-A
Country	US
Kind code	B2
Filing date	May 11, 2014
Priority date	Sep 3, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A communication unit includes at least one divider module arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal, and a plurality of sliced RF modules. Each of the plurality of sliced RF modules includes: an input for receiving a clock signal; a timing synchronization module arranged to receive the divided representation of the RF signal and synchronize the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and at least one logic module operably coupled to the timing synchronization module and arranged to receive the clock signal and a synchronized output from the timing synchronization module. A combiner port is arranged to couple a number of synchronized outputs from the plurality of sliced RF modules.

First claim

What is claimed is:

1. A communication unit comprising:
at least one divider circuit arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal; and
a plurality of sliced RF modules, with each of the plurality of sliced RF modules comprising:
an input for receiving a clock signal;
a timing synchronisation circuit arranged to receive the divided representation of the RF signal and synchronise the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and
at least one logic circuit operably coupled to the timing synchronisation circuit and arranged to receive the clock signal and a synchronised output from the timing synchronisation circuit; wherein,
the synchronised output is operably coupled to a combiner port arranged to couple a number of synchronised outputs from the plurality of sliced RF modules;
wherein the at least one logic circuit is operably coupled to the timing synchronisation circuit, rather than being directly connected to the at least one divider circuit, for reducing current usage in RF communications.

2. The communication unit of claim 1 wherein the timing synchronisation circuit is arranged to output a time-adjusted divided representation of the RF signal.

3. The communication unit of claim 1 wherein the timing synchronisation circuit is at least one flip-flop circuit.

4. The communication unit of claim 3 wherein the at least one flip-flop circuit is a D-type flip flop.

5. The communication unit of claim 1 wherein the timing synchronisation circuit is a driver circuit.

6. The communication unit of claim 1 wherein each sliced RF module comprises the at least one divider circuit.

7. The communication unit of claim 1 wherein the at least one logic circuit comprises a logic AND circuit.

8. The communication unit of claim 1 wherein the RF signal is a local oscillator signal and the at least one divider circuit comprises a divide-by-two circuit.

9. The communication unit of claim 1 wherein the communication unit further comprises a controller arranged to selectively enable one or more of the plurality of sliced RF modules.

10. A sliced radio frequency (RF) module comprising:
an input for receiving from at least one divider circuit a divided representation of a RF signal;
an input for receiving a clock signal;
a timing synchronisation circuit arranged to receive the divided representation of the RF signal and synchronise the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and
at least one logic circuit operably coupled to the timing synchronisation circuit and arranged to receive the clock signal and a synchronised output from the timing synchronisation circuit; and
an output port for outputting a synchronised output to a combiner operably coupleable to at least one further sliced RF module;

wherein the at least one logic circuit is operably coupled to the timing synchronisation circuit, rather than being directly connected to the at least one divider circuit, for reducing current usage in RF communications.

11. The sliced RF module of claim 10 wherein the timing synchronisation circuit is arranged to output a time-adjusted divided representation of the RF signal.

12. The sliced RF module of claim 10 wherein the timing synchronisation circuit is at least one flip-flop circuit.

13. The sliced RF module of claim 12 wherein the at least one flip-flop circuit is a D-type flip flop.

14. The sliced RF module of claim 10 wherein the timing synchronisation circuit is a driver circuit.

15. The sliced RF module of claim 10 wherein the sliced radio frequency module comprises the at least one divider circuit.

16. The sliced RF module of claim 10 wherein the at least one logic circuit comprises a logic AND circuit.

17. The sliced RF module of claim 10 wherein the RF signal is a local oscillator signal and the at least one divider circuit comprises a divide-by-two circuit.

18. The sliced RF module of claim 10 wherein the sliced RF module further comprises a selectable enabling circuit arranged to selectively enable the sliced RF module.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Fong Neric
• Lu Siu-Chuang Ivan
• Chang Chunwei

Classifications

• H04L7/0079 Primary

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