Syncless unit interval variation tolerant PWM receiver circuit, system and method

Patent metadata

Field	Value
Publication number	US-9425781-B2
Application number	US-201414231133-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Mar 29, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.

First claim

What is claimed is:

1. A method of demodulating a pulse width modulation signal, comprising:
receiving the pulse width modulation signal, the pulse width modulation signal having first and second levels;
charging, by a first current source, a first capacitor in response to the pulse width modulation signal changing from the first level to the second level during a first time interval;
charging, by a second current source, a second capacitor in response to the pulse width modulation changing from the second level to the first level during the first time interval; and
demodulating the pulse width modulation signal for the first time interval based on voltages of the first and second capacitors.

2. The method of claim 1 , wherein a sign of the difference between the voltages of the first and second capacitors indicates whether the pulse width modulate signals is communicating a logic 0 or a logic 1 during the first time interval.

3. The method of claim 1 , wherein the pulse width modulation signal includes successive time intervals, the method further including interleaving the receiving of the pulse width modulation signal, the charging of the first capacitor, and the charging of the second capacitor, and demodulating the pulse width modulation signal for each of the successive time intervals.

4. The method of claim 1 , wherein the receiving of the pulse width modulation signal includes:
receiving a low voltage differential signal; and
generating the pulse width modulation signal by converting the low voltage differential signal to a CMOS level signal.

5. The method of claim 1 , wherein the charging of the first capacitor includes generating a first current and the charging of the second capacitor includes generating a second current, the first and second currents being independently generated and matched currents.

6. The method of claim 1 , further comprising:
discharging the first and second capacitors subsequent to the demodulation of the pulse width modulation signal.

7. The method of claim 1 , further comprising:
disconnecting the second current source from the second capacitor in response to the pulse width modulation signal changing from the first level to the second level during the first time interval; and
disconnecting the first current source from the first capacitor in response to the pulse width modulation signal changing from the second level to the first level during the first time interval.

8. The method of claim 1 , wherein the charging of the first capacitor includes providing a first current to the first capacitor, and the charging of the second capacitor includes providing a second current to the second capacitor, the first current being substantially the same as the second current.

9. The method of claim 1 , further comprising holding a charge of the first capacitor during the charging of the second capacitor.

10. A circuit, comprising:
a first capacitor;
a second capacitor;
a receiving circuit configured to receive an input signal carrying a data value and having first and second levels;
a first current source configured to charge the first capacitor in response to the input signal changing from the second level to the first level;
a second current source configured to charge the second capacitor in response to the input signal changing from the first level to the second level; and
a first comparator circuit configured to demodulate the input signal and recover the data value based on a voltage of the first capacitor and a voltage of the second capacitor.

11. The circuit of claim 10 , wherein the voltage of the first capacitor has a first magnitude that is related to a time during which the input signal has the first level, and the voltage of the second capacitor has a second magnitude that is related to a time during which the input signal has the second level.

12. The circuit of claim 10 , wherein the first current source is configured to charge the first capacitor while the input signal has the first level, and the second current source charges the second capacitor while the input signal has the second level.

13. The circuit of claim 10 , wherein the first and second current sources are configured to charge the first and second capacitors, respectively, during a first cycle of the input signal, the demodulation circuit further including:
a third current source configured to charge a third capacitor in response to the input signal changing from the second level to the first level during a second cycle of the input signal that is subsequent to the first cycle;
a fourth current source configured to charge a fourth capacitor in response to the input signal changing from the first level to the second level during the second cycle of the input signal; and
a second comparator circuit configured to recover another data value based on a voltage of the third capacitor and a voltage of the fourth capacitor.

14. The demodulation circuit of claim 10 , wherein the first capacitor has a first maximum capacitance, and the second capacitor has a second maximum capacitance that is substantially equal to the first maximum capacitance.

15. The demodulation circuit of claim 10 , further comprising:
a first switch coupled between the first current source and the first capacitor, the first switch configured to disconnect the first current source from the first capacitor in response to the input signal changing from the first level to the second level; and
a second switch coupled between the second current source and the second capacitor, the second switch configured to disconnect the second current source from the second capacitor in response to the input signal changing from the second level to the first level during the first time interval.

16. A system, comprising:
a receiving circuit configured to receive an input signal carrying a plurality of data values, the input signal having first and second levels;
a plurality of demodulation circuits, each of the plurality of demodulation circuits including:
a first capacitor;
a second capacitor;
a first current source configured to charge the first capacitor in response to the input signal changing from the first level to the second level;
a second current source configured to charge the second capacitor in response to the input signal changing from the second level to the first level; and
a comparator circuit configured demodulate the input signal and recover a data value of the plurality of data values based on voltages of the first and second capacitors.

17. The system of claim 16 , wherein each of the plurality of demodulation circuits includes a microprocessor or a microcontroller.

18. The system of claim 16 , wherein the plurality of demodulation circuits are disposed on a same die.

19. The system of claim 16 , further comprising:
a control circuit configured to select a first demodulation circuit of the plurality of demodulation circuits to demodulate the input signal for a first time interval, and select a second demodulation circuit of the plurality of demodulation circuits to demodulate the input signal for a second time interval that is subsequent to the first time interval.

20. The system of claim 16 , wherein first and second demodulation circuits of the plurality of demodulation circuits are disposed on respective dies.

21. A method, comprising:
receiving an input signal carrying a first data value during a first time interval, the input signal having first and second levels;
charging, by a first c

Assignees

• St Microelectronics Int Nv

Inventors

• Nandy Tapas
• Jain Anchal

Classifications

• H03K9/08 Primary

  of duration- or width-mudulated pulses {or of duty-cycle modulated pulses} · CPC title