Fin field effect transistor (FinFET) device structure with Ge-doped inter-layer dielectric (ILD) structure

Patent metadata

Field	Value
Publication number	US-9425317-B1
Application number	US-201514632987-A
Country	US
Kind code	B1
Filing date	Feb 26, 2015
Priority date	Feb 26, 2015
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending above the substrate. The FinFET device structure includes an isolation structure, and the fin structure is embedded in the isolation structure. The FinFET device structure also includes a gate structure formed on a middle portion of the fin structure. The gate structure has a top portion and bottom portion, and the bottom portion is wider than the top portion. The FinFET device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.

First claim

What is claimed is:

1. A fin field effect transistor (FinFET) device structure,
comprising:
a substrate;
a fin structure extending above the substrate;
an isolation structure, wherein the fin structure is embedded in the isolation structure;
a gate structure formed on a middle portion of the fin structure, wherein the gate structure has a top portion with a top width in a direction parallel to the fin and bottom portion with a bottom width in a direction parallel to the fin, and the bottom width is wider than the top width;
a source/drain (S/D) structure formed adjacent to the gate structure; and
an inter-layer dielectric (ILD) structure formed adjacent to the gate structure, wherein the ILD structure has a gradient germanium (Ge) concentration.

2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the bottom portion of the gate structure has a trumpet-like, diamond-like, breaker-like, or vase-like shape.

3. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the gradient germanium (Ge) concentration is increased from a top surface to a bottom surface of the inter-layer dielectric (ILD) structure.

4. The fin field effect transistor (FinFET) device structure as claimed in claim 3 , wherein a germanium (Ge) concentration difference between the top surface and the bottom surface of the inter-layer dielectric (ILD) structure is in a range from about 0.1% to about 50%.

5. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein bottom portion of the gate structure is sloped to a top surface of the isolation structure.

6. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
a spacer formed adjacent to the gate structure, wherein the spacer has a top portion and a bottom portion, and the bottom portion of the spacer is sloped to a top surface of the isolation structure.

7. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the top portion of the gate structure has vertical sidewalls, and the bottom portion has sloped sidewalls.

8. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein a width of the bottom portion is increased from top to down.

9. A fin field effect transistor (FinFET) device structure, comprising:
a substrate;
a fin structure extending above the substrate;
a gate structure transversely overlying the fin structure, wherein the gate structure has structure a top portion and bottom portion, the top portion of the gate structure has vertical sidewalls, and the bottom portion has sloped sidewalls;
a source/drain (S/D) structure formed adjacent to the gate structure; and
an inter-layer dielectric (ILD) structure formed adjacent to the gate structure, wherein the inter-layer dielectric (ILD) structure has a gradient germanium (Ge) concentration.

10. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , wherein the bottom portion of the gate structure has a trumpet-like, diamond-like, breaker-like, or vase-like shape.

11. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , wherein a width of the bottom portion of the gate structure is increased.

12. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , further comprising:
an isolation structure, wherein the fin structure is embedded in the isolation structure, and the bottom portion of the gate structure is sloped to a top surface of the isolation structure.

13. The fin field effect transistor (FinFET) device structure as claimed in claim 12 , wherein the fin structure of the gate structure has a fin height which protrudes from the isolation structure, and the bottom portion has a height which is one-third of the fin height.

14. The fin field effect transistor (FinFET) device structure as claimed in claim 12 , further comprising:
a spacer formed adjacent to the gate structure, wherein the spacer has a top portion and a bottom portion, and the bottom portion of the spacer is sloped to a top surface of the isolation structure.

15. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , wherein the gradient germanium (Ge) concentration is increased from a top surface to a bottom surface of the inter-layer dielectric (ILD) structure.

16. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
receiving a substrate;
forming a fin structure on the substrate;
forming an isolation structure on the substrate, wherein the fin structure is embedded in the isolation structure;
forming a dummy gate structure on a middle portion of the fin structure;
forming a source/drain (S/D) structure adjacent to the dummy gate structure;
forming an inter-layer dielectric (ILD) structure formed adjacent to the dummy gate structure, wherein the ILD structure has a gradient germanium (Ge) concentration;
removing the dummy gate structure to form a trench;
removing a portion of the ILD structure to enlarge a width of a bottom portion of the trench; and
filling a gate structure into the trench.

17. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 16 , wherein forming the ILD structure comprises:
mixing a germanium-containing compound and a silicon-containing compound;
performing a deposition process on the dummy gate structure and the fin structure.

18. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 16 , wherein the trench has a top portion and a bottom portion, and the bottom portion of the trench is wider than the top portion of the trench after removing the portion of the ILD structure.

19. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 16 , further comprising:
forming a spacer lining the sidewalls of the trench, before filling the gate structure into the trench.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wen Tsung-Yao
• Chiou Yao-De
• Wang Sheng-Chen
• Yeong Sai-Hooi

Classifications

• H10D30/6217 Primary

  having non-uniform gate electrodes, e.g. gate conductors having varying doping · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title