Method for growing an epitaxial film on a phosphorous-doped silicon wafer

Patent metadata

Field	Value
Publication number	US-9425264-B2
Application number	US-201313925267-A
Country	US
Kind code	B2
Filing date	Jun 24, 2013
Priority date	Jun 29, 2012
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step.

First claim

What is claimed is:

1. A manufacturing method of an epitaxial silicon wafer provided by forming an epitaxial film on a surface of a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 mΩ·cm, the method comprising:
forming an oxidation film on a backside of a silicon wafer cut out from a single crystal ingot prepared by a Czochralski process;
removing the oxidation film present at an outer periphery of the silicon wafer;
argon annealing in which a heat treatment is applied on the silicon wafer after removing the oxidation film in a gas atmosphere consisting of argon at a temperature in a range from 1200 to 1220 degrees C.;
applying a heat treatment under a hydrogen gas atmosphere on the silicon wafer after being subjected to the argon annealing; and
growing the epitaxial film on the surface of the silicon wafer after applying the heat treatment under the hydrogen gas atmosphere.

2. The manufacturing method of an epitaxial silicon wafer according to claim 1 , further comprising:
performing a pit-evaluation heat treatment on an evaluation silicon wafer cut out from the single crystal ingot, all of steps from the forming of the oxidation film on the backside to the growing of the epitaxial film being performed on the silicon wafer cut out from a section including a cut point of the evaluation silicon wafer when pits are observed on a surface of the evaluation silicon wafer.

3. The manufacturing method of an epitaxial silicon wafer according to claim 1 , wherein the silicon wafer cut out from the single crystal ingot is cut out from a section of the single crystal ingot that has been heated in a temperature range from 570±70 degrees C. for more than 200 minutes during a manufacturing process of the single crystal ingot.

4. The manufacturing method of an epitaxial silicon wafer according to claim 1 , wherein a resistivity of the silicon wafer is less than 0.8 mΩ·cm.

5. The manufacturing method of an epitaxial silicon wafer according to claim 4 , wherein the resistivity of the silicon wafer is 0.6 mΩ·cm or more.

6. The manufacturing method of an epitaxial silicon wafer according to claim 1 , further comprising:
manufacturing the single crystal ingot by the Czochralski process with an addition of germanium so that a concentration of the germanium in the silicon wafer falls within a range from 3.70×10 19 atoms/cm 3 to 2.93×10 20 atoms/cm 3 .

7. The manufacturing method of an epitaxial silicon wafer according to claim 1 , wherein in the argon annealing, heat is applied so that clusters formed by bonded oxygen and phosphorus in the silicon wafer are subjected to a solution treatment and phosphorus on the surface of the silicon wafer is out-diffused.

8. The manufacturing method of an epitaxial silicon wafer according to claim 7 , wherein a heat treatment time of the argon annealing is in a range from 30 minutes to 120 minutes.

9. The manufacturing method of an epitaxial silicon wafer according to claim 8 , wherein a heat treatment time of the argon annealing is in a range from 60 minutes to 120 minutes.

Assignees

• Sumco Corp
• Sumco Techxiv Corp

Inventors

• Kawashima Tadashi
• Nonaka Naoya
• Shinagawa Masayuki
• Uesono Gou

Classifications

• H10P36/03

  within silicon bodies · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title