Glass frit wafer bond protective structure

Patent metadata

Field	Value
Publication number	US-9425115-B2
Application number	US-201314104658-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Apr 30, 2012
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.

First claim

What is claimed is:

1. A bonded semiconductor device comprising:
a device substrate with a semiconductor device located with respect to one side of the device substrate;
a cap substrate overlying the one side of the device substrate and the semiconductor device, wherein the cap substrate includes a semiconductor material;
a glass frit bond ring between the device substrate and the cap substrate, wherein the cap substrate is bonded to the device substrate at least by the glass frit bond ring;
an electrically conductive ring between the device substrate and the cap substrate, wherein the electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer ring around the semiconductor device.

2. The device of claim 1 , wherein the electrically conductive ring prevented glass frit of the glass frit bond ring from flowing in an area where the semiconductor device is located.

3. The device of claim 1 , wherein the electrically conductive ring is discontinuous around the semiconductor device.

4. The device of claim 1 , wherein the electrically conductive ring is continuous around the semiconductor device.

5. The device of claim 1 wherein the semiconductor device is hermetically sealed at least by the cap substrate being bonded by the glass frit bond ring to the device substrate.

6. The device of claim 1 , wherein the electrically conductive ring provides electrical grounding for the cap substrate.

7. The device of claim 1 , wherein the electrically conductive ring includes a poly silicon portion, a mono crystalline portion, and a metal portion in between the poly silicon portion and the mono crystalline portion.

8. The device of claim 7 wherein the mono crystalline portion of the electrically conductive ring has a net conductivity dopant that is greater than a portion of the cap substrate made of mono crystalline silicon.

9. The device of claim 1 , wherein the glass frit bond ring includes a ring of glass frit material and a ring of poly silicon in contact with the ring of glass frit material.

10. The device of claim 1 further comprising:
an electrically conductive pad located with respect to the one side of the device substrate located outside the electrically conductive ring and the glass frit bond ring.

11. The device of claim 1 wherein the device substrate includes a layer of dielectric material located over a layer of semiconductor material, the layer of dielectric material including an opening wherein the electrically conductive ring is in electrical contact with the layer of semiconductor material through the opening.

12. The device of claim 2 , wherein the electrically conductive ring provides electrical grounding for the cap substrate.

13. The device of claim 5 , wherein the electrically conductive ring provides electrical grounding for the cap substrate.

14. The device of claim 6 , wherein the electrically conductive ring includes a poly silicon portion, a mono crystalline portion, and a metal portion in between the poly silicon portion and the mono crystalline portion.

15. The device of claim 14 wherein the mono crystalline portion of the electrically conductive ring has a net conductivity dopant that is greater than a portion of the cap substrate made of mono crystalline silicon.

16. The device of claim 2 , wherein the glass frit bond ring includes a ring of glass frit material and a ring of poly silicon in contact with the ring of glass frit material.

17. The device of claim 5 , wherein the glass frit bond ring includes a ring of glass frit material and a ring of poly silicon in contact with the ring of glass frit material.

18. The device of claim 5 wherein the device substrate includes a layer of dielectric material located over a layer of semiconductor material, the layer of dielectric material including an opening wherein the electrically conductive ring is in electrical contact with the layer of semiconductor material through the opening.

19. The device of claim 6 wherein the device substrate includes a layer of dielectric material located over a layer of semiconductor material, the layer of dielectric material including an opening wherein the electrically conductive ring is in electrical contact with the layer of semiconductor material through the opening.

20. The device of claim 7 wherein the device substrate includes a layer of dielectric material located over a layer of semiconductor material, the layer of dielectric material including an opening wherein the electrically conductive ring is in electrical contact with the layer of semiconductor material through the opening.

21. The device of claim 1 wherein the cap substrate and the device substrate are physically coupled through the electrically conductive ring.

Assignees

• Freescale Semiconductor Inc

Inventors

• Montez Ruben B
• Steimle Robert F

Classifications

• H10W76/18

  Insulating materials, e.g. resins, glasses or ceramics · CPC title

• H10W76/15

  Containers comprising an insulating or insulated base · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/90

  Bond pads, in general · CPC title