Complementary metal oxide semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9425104-B2
Application number	US-201414259569-A
Country	US
Kind code	B2
Filing date	Apr 23, 2014
Priority date	Sep 6, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a silicon substrate, and a first layer including a group III-V material is disposed on the buffer layer. A second layer including a group IV material is disposed on the buffer layer or the silicon substrate while being spaced apart from the first layer.

First claim

What is claimed is:

1. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device, the method comprising: forming a buffer layer directly on a silicon substrate, the buffer layer including at least one of a Group IV and a Group III-V material; forming a material layer for an n-type transistor on the buffer layer; etching the material layer for the n-type transistor to form a first layer for the n-type transistor and a first pattern; forming an insulating layer on the first layer and the first pattern; etching the insulating layer to form a second pattern for selective growth, the second pattern exposing the buffer layer; selectively growing a second layer for a p-type transistor in the second pattern, the second layer contacting the buffer layer; and planarizing the second layer and the insulating layer to expose the first layer; wherein the first layer is isolated from the second layer by the insulating layer.

2. The method of claim 1 , wherein the buffer layer is formed of at least one of indium (In), gallium (Ga), and aluminum (Al), and at least one of arsenic (As), phosphorus (P), and stibium (Sb).

3. The method of claim 2 , wherein the buffer layer is formed of at least one of InP, InAs, InSb, GaAs, GaP, GaSb, AlP, AlAs, AlSb, InAlAs, InGaP, GaAsP, InGaAsP, and InGaAlAs.

4. The method of claim 2 , wherein the buffer layer is doped with an n-type dopant.

5. The method of claim 1 , wherein the buffer layer is formed of at least one of SiGe, GeSn, and germanium (Ge).

6. The method of claim 1 , wherein the first layer is formed of a Group III-V material.

7. The method of claim 1 , wherein the first layer is formed of at least one of InGaAs, InP, InSb, InGaSb, GaSb, and InAs.

8. The method of claim 1 , wherein the second layer is formed of a Group IV material.

9. The method of claim 8 , wherein the second layer is formed of Ge.

10. The method of claim 1 , wherein the n-type transistor comprises an n-type metal oxide semiconductor field effect transistor (MOSFET).

11. The method of claim 1 , wherein the p-type transistor comprises a p-type MOSFET.

12. The method of claim 1 , wherein the first layer and the second layer are channel layers.

13. The method of claim 1 , wherein the forming the first pattern includes etching the material layer to expose a portion of the buffer layer.

14. The method of claim 1 , wherein the insulating layer is formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

15. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device, the method comprising: forming a buffer layer directly on a substrate, the buffer layer including at least one of a Group IV and a Group III-V material; forming a first material layer on the buffer layer, the first material layer including a group III-V material; etching the first material layer and the buffer layer to form a first layer and a first pattern, the first pattern exposing the substrate; forming an insulating layer on the first layer and the first pattern; etching the insulating layer to form a second pattern, the second pattern exposing the substrate; selectively growing a second material layer in the second pattern, the second material layer including a group IV material; and planarizing the second layer and the insulating layer to expose the first layer; wherein the first layer is isolated from the second layer by the insulating layer.

16. The method of claim 15 , wherein:
the first material layer includes at least one of InGaAs, InP, InGaSb, GaSb, InAs, GaAs, and InSb; and
the second material layer includes Ge.

17. The method of claim 15 , wherein selectively growing the second material layer comprises growing the second material layer on the buffer layer.

Assignees

• Yang Moon-Seung
• Uddin Mohammad Rakib
• Lee Myoung-Jae
• Lee Sang-Moon
• Lee Sung-Hun
• Cho Seong-Ho
• Samsung Electronics Co Ltd

Inventors

• Yang Moon-Seung
• Uddin Mohammad Rakib
• Lee Myoung-Jae
• Lee Sang-Moon
• Lee Sung-Hun
• Cho Seong-Ho

Classifications

• H10D84/0165 Primary

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/05 Primary

  using Group III-V technology · CPC title

• H10D84/08

  using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title