Forming arsenide-based complementary logic on a single substrate

Patent metadata

Field	Value
Publication number	US-9006707-B2
Application number	US-71219107-A
Country	US
Kind code	B2
Filing date	Feb 28, 2007
Priority date	Feb 28, 2007
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a silicon (Si) substrate;
an n-type semiconductor device formed over the SI substrate from a stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer;
a p-type semiconductor device formed over the Si substrate from a stack including the first buffer layer, the second buffer layer formed over the first buffer layer, a second device layer formed over the second buffer layer; and
an isolation interposed between the n-type semiconductor device and the p-type semiconductor device;
wherein the first device layer comprises:
a lower barrier layer that is inverse step graded within the lower barrier layer itself, the lower barrier layer comprising one of the indium aluminium arsenide (In x Al 1-x As) an indium gallium aluminium arsenide (InGaAlAs); and
a quantum well layer, formed over the lower barrier layer, comprising indium gallium arsenide (In x Ga 1-x As).

2. The apparatus of claim 1 , wherein the first device layer comprises:
a spacer layer formed over the quantum well layer;
the Si-modulation delta-doped layer formed over the spacer layer; and
an upper barrier layer formed over the Si-modulation delta-doped layer.

3. The apparatus of claim 1 , wherein x of IN x Ga 1-x As is between approximately 0.5 and 0.8.

4. The apparatus of claim 2 , wherein the second device layer comprises:
the lower barrier layer:
the quantum well layer formed over the lower barrier layer comprising In x Ga 1-x As;
the spacer layer formed over the quantum well layer;
the Be-modulation delta-doped layer formed over the spacer layer; and
the upper barrier layer formed over the Be-modulation delta-doped layer.

5. The apparatus of claim 4 , wherein x of In x Ga 1-x As is between approximately 0.5 and 0.8.

6. The apparatus of claim 1 , wherein the Si substrate comprises an off-oriented substrate.

7. The apparatus of claim 4 , further comprising a gate dielectric formed over a gate recess in the upper barrier layer, and a gate electrode formed over the gate dielectric.

8. The apparatus of claim 4 , wherein the n-type and p-type semiconductor devices are each no more than 50 nm in height and each having a switching frequency greater than 500 GHz.

9. The apparatus of claim 4 , wherein x of In x Ga 1-x As is at least 0.51.

10. The apparatus of claim 6 , wherein the off-oriented substrate is cut at an angle generally between 2 and 12 degrees towards the ( 110 ) direction.

11. The apparatus of claim 2 , wherein the lower barrier layer is graded within the lower barrier layer itself so aluminum increases in a direction going away from the substrate.

12. The apparatus of claim 4 , wherein:
the lower barrier layer is graded within the lower barrier layer itself so aluminum increases in a direction going away from the substrate;
the space layer formed over the quantum well layer in the first device layer includes In x Al 1-x As; and
the spacer layer formed over the quantum well layer in the second device layer includes InAlAs.

13. The apparatus of claim 1 , wherein the lower barrier layer is graded within the lower barrier layer itself so aluminum increases in a direction going away from the substrate.

14. The apparatus of claim 1 , wherein the lower barrier consists of In x Al 1-x As.

15. The apparatus of claim 1 , wherein the lower barrier consists of InGaAlAs.

16. An apparatus comprising:
an n-type semiconductor device, formed over a silicon (Si) substrate, including a second buffer layer formed over a first buffer layer and under a first device layer; and
a p-type semiconductor device, formed over the Si substrate, including the second buffer layer formed over the first buffer layer and under a second device layer;
wherein the first device layer comprises (a) a barrier layer inverse step graded within the barrier layer itself and comprising one of indium aluminium arsenide (In x Al 1-x As) and indium gallium aluminium arsenide (InGaAlAs); and (b) a quantum well layer, formed over the barrier layer, comprising indium gallium arsenide (In x Ga 1-x As).

17. The apparatus of claim 16 , wherein the first device layer comprises a Si-modulation delta-doped layer.

18. The apparatus of claim 17 , wherein the second device layer comprises the barrier layer, the quantum well layer. And the Be-modulation delta-doped layer.

19. The apparatus of claim 16 . wherein the barrier layer consists of IN x Al 1-x As.

20. The apparatus of claim 16 , wherein the barrier layer consists of InGaAlAs.

Assignees

• Hudait Mantu K
• Kavalieros Jack T
• Datta Suman
• Radosavljevic Marko
• Intel Corp

Inventors

• Hudait Mantu K
• Kavalieros Jack T
• Datta Suman
• Radosavljevic Marko

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/3221

  Arsenides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/05

  using Group III-V technology · CPC title