Tightly coupled multiprocessor system

Patent metadata

Field	Value
Publication number	US-9424223-B2
Application number	US-201313910282-A
Country	US
Kind code	B2
Filing date	Jun 5, 2013
Priority date	Jun 8, 2012
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

The tightly coupled multiprocessor system includes a plurality of main processors. The main processors are connected via an inter-processor interface. Each of the main processors includes at least one pair of an expansion slot for installing a coprocessor and an expansion slot for installing an external interface card.

First claim

The invention claimed is:

1. A tightly coupled multiprocessor system comprising a plurality of main processors connected via an inter-processor interface, wherein
each of the main processors includes at least one pair of an expansion slot for installing a coprocessor and an expansion slot for installing an external interface card, wherein
the main processors includes a first main processor and a second main processor,
the first main processor is connected with a first main memory, a first expansion slot for installing a coprocessor, a first expansion slot for installing an external interface card, and the inter-processor interface,
the second main processor is connected with a second main memory, a second expansion slot for installing a coprocessor, a second expansion slot for installing an external interface card, and the inter-processor interface,
the first main processor includes:
at least one first processor core;
a first cache memory connected with the first processor core;
a first main memory controller connected with the first main memory;
a plurality of first input/output controllers connected with the first expansion slot for installing a coprocessor and the first expansion slot for installing an external interface card; and
a first crossbar switch connected with the first cache memory, the first main memory controller, the first input/output controllers, and the inter-processor interface, and

the second main processor includes:
at least one second processor core;
a second cache memory connected with the second processor core;
a second main memory controller connected with the second main memory;
a plurality of second input/output controllers connected with the second expansion slot for installing a coprocessor and the second expansion slot for installing an external interface card; and
a second crossbar switch connected with the second cache memory, the second main memory controller, the second input/output controllers, and the inter-processor interface.

2. The tightly coupled multiprocessor system, according to claim 1 , wherein
the number of lanes of the expansion slot for installing a coprocessor and the number of lanes of the expansion slot for installing an external interface card are the same.

3. The tightly coupled multiprocessor system, according to claim 1 , wherein
the expansion slot for installing a coprocessor and the expansion slot for installing an external interface card are slots compatible with PCI Express.

4. The tightly coupled multiprocessor system, according to claim 1 , wherein
the number of lanes of the expansion slot for installing a coprocessor and the expansion slot for installing an external interface card is 16.

5. The tightly coupled multiprocessor system, according to claim 1 , wherein
each of the main processors includes a first input/output controller to which the expansion slot for installing a coprocessor is connected, and a second input/output controller to which the expansion slot for installing an external interface card is connected.

6. The tightly coupled multiprocessor system, according to claim 5 , wherein
DMA transfer is performed between a coprocessor connected to the expansion slot for installing a coprocessor, and an external device connected to an external interface card connected to the expansion slot for installing an external interface card, the expansion slot for installing an external interface card forming a pair with the expansion slot for installing a coprocessor.

7. The tightly coupled multiprocessor system, according to claim 1 , wherein
the main processor includes a PCI Express-compatible switch in which the expansion slot for installing a coprocessor and the expansion slot for installing an external interface card, forming a pair with the expansion slot for installing a coprocessor, are connected to different downstream ports respectively.

8. The tightly coupled multiprocessor system, according to claim 7 , wherein
the main processor includes an input/output controller connected to an upstream port of the switch.

9. The tightly coupled multiprocessor system, according to claim 7 , wherein
DMA transfer is performed via the switch between a coprocessor connected to the expansion slot for installing a coprocessor, and an external device connected to an external interface card connected to the expansion slot for installing an external interface card, the expansion slot for installing an external interface card forming a pair with the expansion slot for installing a coprocessor.

10. The tightly coupled multiprocessor system, according to claim 6 , wherein
the coprocessor is able to execute an instruction which is the same as an instruction to be executed by the main processor.

11. The tightly coupled multiprocessor system, according to claim 6 , wherein
the coprocessor is able to execute a main routine.

12. A method of controlling a tightly coupled multiprocessor system including a first main processor and a second main processor, the first main processor including a first expansion slot for installing a coprocessor and a first expansion slot for installing an external interface card, the second main processor being connected with the first main processor via an inter-processor interface and including a second expansion slot for installing a coprocessor and a second expansion slot for installing an external interface card, the method comprising:
allowing to perform first data transfer by a DMA method between a first coprocessor connected to the first expansion slot for installing a coprocessor, and a first external device connected to a first external interface card connected to the first expansion slot for installing an external interface card; and
allowing to perform second data transfer by a DMA method between a second coprocessor connected to the second expansion slot for installing a coprocessor, and a second external device connected to a second external interface card connected to the second expansion slot for installing an external interface card, wherein

the main processors includes a first main processor and a second main processor,
the first main processor is connected with a first main memory, a first expansion slot for installing a coprocessor, a first expansion slot for installing an external interface card, and the inter-processor interface,
the second main processor is connected with a second main memory, a second expansion slot for installing a coprocessor, a second expansion slot for installing an external interface card, and the inter-processor interface,
the first main processor includes:
at least one first processor core;
a first cache memory connected with the first processor core;
a first main memory controller connected with the first main memory;
a plurality of first input/output controllers connected with the first expansion slot for installing a coprocessor and the first expansion slot for installing an external interface card; and
a first crossbar switch connected with the first cache memory, the first main memory controller, the first input/output controllers, and the inter-processor interface, and

the second main processor includes:
at least one second processor core;
a second cache memory connected with the second processor core;
a second main memory controller connected with the second main memory;
a plurality of second input/output controllers connected with the second expansion slot for installing a coprocessor and the second expansion slot for installing an external interface card; and
a second crossbar switch connected with the second cache memory, the second main memory controller, the second input/output controll

Assignees

• Nec Corp

Inventors

• Nasu Yasuyuki

Classifications

• G06F13/409 Primary

  Mechanical coupling (back panels H05K7/1438) · CPC title