Low-power open-circuit detection system

Patent metadata

Field	Value
Publication number	US-9419614-B2
Application number	US-201514843997-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Jan 16, 2015
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An open-circuit detection system for an integrated circuit (IC) includes a wire (e.g., part of a wire mesh for device protection) and circuitry for detecting open-circuit conditions in the wire. A first signal generator (e.g., a linear-feedback shift register) applies a binary sequence to a first end of the wire. Switched resistors are connected between a second end of the wire and both a voltage supply and ground. A comparator compares the binary sequence and a signal based on the voltage at the second end of the wire to check for the open-circuit condition. Logic circuitry closes one of the first and second switches as a function of a value in the binary sequence. The comparator checks for the open-circuit condition in the wire randomly and intermittently, which reduces power consumption.

First claim

The invention claimed is:

1. Detection circuitry for detecting an open-circuit condition in a wire, the detection circuitry comprising:
a first signal generator that generates and applies a binary sequence to a first end of the wire;
a first series combination of a first resistor and a first switch connected between a voltage supply node and a second end of the wire;
a second series combination of a second resistor and a second switch connected between the second end of the wire and a ground node;
comparator circuitry that compares (i) the binary sequence generated by the first signal generator and (ii) a signal based on the voltage at the second end of the wire to check for an open-circuit condition in the wire; and
logic circuitry that receives the binary sequence from the first signal generator and closes one of the first and second switches as a function of a value in the binary sequence, wherein the comparator circuitry checks for the open-circuit condition in the wire only when one of the first and second switches is closed by the logic circuitry.

2. The detection circuitry of claim 1 , wherein the logic circuitry allows only one of the first and second switches to be closed at a time.

3. The detection circuitry of claim 1 , wherein the comparator circuitry checks for the open-circuit condition in the wire randomly and intermittently only when one of the first and second switches is closed by the logic circuitry.

4. The detection circuitry of claim 1 , wherein the binary sequence generated by the first signal generator is a random or pseudo-random binary sequence.

5. The detection circuitry of claim 4 , wherein the first signal generator comprises a linear-feedback shift register (LFSR).

6. The detection circuitry of claim 1 , wherein the comparator circuitry comprises:
a de-glitch circuit connected to receive and de-glitch the voltage at the second end of the wire to generate a de-glitched signal; and
a comparator connected to compare the binary sequence generated by the first signal generator and the de-glitched signal to check for the open-circuit condition in the wire.

7. The detection circuitry of claim 1 , wherein the logic circuitry comprises:
a first AND gate connected to control the first switch based on a value in the binary sequence and a logic signal that intermittently allows one of the first and second switches to be closed; and
a second AND gate connected to control the second switch based on the value in the binary sequence and the logic signal.

8. The detection circuitry of claim 7 , wherein the logic signal randomly and intermittently allows one of the first and second switches to be closed.

9. The detection circuitry of claim 7 , wherein the logic circuitry further comprises an inverter connected to invert the value of the binary sequence applied to the first AND gate.

10. The detection circuitry of claim 7 , wherein the logic circuitry further comprises:
a second signal generator that generates a random N-bit value; and
a second comparator that compares the random N-bit value to a specified N-bit value to generate the logic value, wherein the logic value allows one of the first and second switches to be closed only when the random N-bit value matches the specified N-bit value.

11. The detection circuitry of claim 10 , wherein the specified N-bit value is all 0s.

12. The detection circuitry of claim 10 , wherein the second signal generator is an LFSR that generates the random N-bit value based on N least significant bits within the LFSR.

13. The detection circuitry of claim 1 , wherein the wire is part of a wire mesh used to provide security for an integrated circuit device.

14. The detection circuitry of claim 13 , wherein the detection circuitry is implemented in protected layers of an integrated circuit die within the integrated circuit device.

15. The detection circuitry of claim 1 , wherein:
the logic circuitry allows only one of the first and second switches to be closed at a time;
the comparator circuitry checks for the open-circuit condition in the wire randomly and intermittently only when one of the first and second switches is closed by the logic circuitry;
the binary sequence generated by the first signal generator is a random or pseudo-random binary sequence;
the first signal generator comprises a first LFSR;
the comparator circuitry comprises:
a de-glitch circuit connected to receive and de-glitch the voltage at the second end of the wire to generate a de-glitched signal; and
a first comparator connected to compare the binary sequence generated by the first signal generator and the de-glitched signal to check for the open-circuit condition in the wire;

the logic circuitry comprises:
a first AND gate connected to control the first switch based on the value in the binary sequence and a logic signal that randomly and intermittently allows one of the first and second switches to be closed;
a second AND gate connected to control the second switch based on the value in the binary sequence and the logic signal;
an inverter connected to invert the value of the binary sequence applied to the first AND gate;
a second LFSR that generates a random N-bit value based on N least significant bits within the LFSR; and
a second comparator that compares the random N-bit value to a specified N-bit value having all 0s to generate the logic value, wherein the logic value allows one of the first and second switches to be closed only when the random N-bit value has all 0s;

the wire is part of a wire mesh used to provide security for an integrated circuit device; and
the detection circuitry is implemented in protected layers of an integrated circuit within the integrated circuit device.

Assignees

• Freescale Semiconductor Inc

Inventors

• Wang Yong

Classifications

• H10W42/405

  using active circuits · CPC title

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• G06F21/87

  by means of encapsulation, e.g. for integrated circuits · CPC title

• G06F21/86

  Secure or tamper-resistant housings · CPC title

• H03K19/003 Primary

  Modifications for increasing the reliability {for protection} · CPC title