Anti-tamper system based on dual random bits generators for integrated circuits

Patent metadata

Field	Value
Publication number	US-9323957-B2
Application number	US-201414187146-A
Country	US
Kind code	B2
Filing date	Feb 21, 2014
Priority date	Mar 1, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

An apparatus includes a mesh block, a first number generator configured to generate a first number, a second number generator configured to generate a second number, and a comparator block configured to compare the first number with the second number and generate an output signal from the mesh block. The output signal indicates an occurrence of an unauthorized activity on the mesh block.

First claim

What is claimed is:

1. A method comprising:
generating first and second pseudo-random numbers using first and second pseudo-random number generators (PRNGs) in an electronic mesh block, respectively;
transmitting a first plurality of pseudo-random signals indicating the first pseudo-random number through a first plurality of mesh wires to a mesh buffer;
converting the first plurality of pseudo-random signals into a first plurality of input signals;
comparing the first plurality of input signals with a second plurality of input signals indicating the second pseudo-random number to generate an output signal from the electronic mesh block;
generating a clock tamper detect signal in a clock tamper detector;
setting the clock tamper detect signal to a logic value at a first time; and
setting the clock tamper detect signal to a result of an OR operation at a second time subsequent to the first time,
wherein the output signal indicates an occurrence of an unauthorized activity on the electronic mesh block, and
wherein converting the first plurality of pseudo-random signals into the first plurality of input signals comprises rearranging and inverting the first plurality of pseudo-random signals to generate a plurality of modified signals using the mesh buffer.

2. The method of claim 1 , wherein the first and second pseudo-random numbers are generated using first and second linear-feedback shift registers (LFSRs), respectively.

3. The method of claim 1 , further comprising transmitting the plurality of modified signals to an inverting block through a second plurality of mesh wires.

4. The method of claim 1 , wherein converting the first plurality of pseudo-random signals into the first plurality of input signals further comprises:
inverting the plurality of modified signals to generate the first plurality of input signals, and
wherein the first plurality of input signals have logic values corresponding to those of the first plurality of pseudo-random signals, respectively.

5. The method of claim 4 , wherein comparing the first plurality of input signals with the second plurality of input signals comprises comparing the first plurality of input signals with the second plurality of input signals in parallel.

6. The method of claim 3 , further comprising:
outputting first one of the plurality of modified signals from the mesh buffer via first one of the second plurality of mesh wires extending from the mesh buffer; and
outputting second one of the plurality of modified signals from the mesh buffer via second one of the second plurality of mesh wires.

7. The method of claim 1 , wherein the electronic mesh block is a first electronic mesh block and the output signal is a first output signal, the method further comprising:
generating third and fourth pseudo-random numbers using third and fourth PRNGs in a second electronic mesh block, respectively;
comparing a third plurality of input signals with a fourth plurality of input signals indicating the fourth pseudo-random number to generate a second output signal from the second electronic mesh block, wherein the second output signal indicates an occurrence of an unauthorized activity on the second electronic mesh block; and
performing the OR operation on the first and second output signals in the clock tamper detector.

8. The method of claim 7 , wherein the second time corresponds to a rising edge of a clock signal received by the clock tamper detector.

9. An apparatus comprising:
an electronic mesh block;
a first pseudo-random number generator (PRNG) configured to generate a first pseudo-random number;
a second PRNG configured to generate a second pseudo-random number;
a first plurality of mesh wires configured to transmit a first plurality of pseudo-random signals indicating the first pseudo-random number;
a mesh buffer and an inverting block configured to convert the first plurality of pseudo-random signals into a first plurality of input signals;
a comparator configured to compare the first plurality of input signals with a second plurality of input signals indicating the second pseudo-random number and generate an output signal from the electronic mesh block, the output signal indicating an occurrence of an unauthorized activity on the electronic mesh block; and
a clock tamper detector to generate a clock tamper detect signal, to set the clock tamper detect signal to a logic value at a first time, and to set the clock tamper detect signal to a result of an OR operation at a second time subsequent to the first time,
wherein the first PRNG, the second PRNG, and the comparator are provided in the electronic mesh block, and
wherein the mesh buffer includes a plurality of inverters configured to rearrange and invert the first plurality of pseudo-random signals to generate a plurality of modified signals.

10. The apparatus of claim 9 , wherein the first and second pseudo-random numbers are generated using first and second linear-feedback shift registers (LFSRs), respectively, and
wherein the second PRNG is included in a comparator block, the comparator block further including the comparator and the inverting block.

11. The apparatus of claim 9 , further comprising
a second plurality of mesh wires configured to transmit the plurality of modified signals to the inverting block.

12. The apparatus of claim 11 , wherein two neighboring wires among the first and second plurality of mesh wires are spaced 0.4 μm apart from each other.

13. The apparatus of claim 9 , wherein the inverting block is configured to invert the plurality of modified signals to generate the first plurality of input signals, the first plurality of input signals having logic values corresponding to those of the first plurality of pseudo-random signals, respectively.

14. The apparatus of claim 13 , wherein the comparator includes an iterative network having a plurality of cells, each cell receiving a first input signal among the first plurality of input signals and a second input signal among the second plurality of input signals, the first and second input signals indicating a pair of corresponding binary numbers.

15. The apparatus of claim 11 , wherein the mesh buffer outputs first one of the plurality of modified signals via first one of the second plurality of mesh wires, and outputs second one of the plurality of modified signals via second one of the second plurality of mesh wires.

16. The apparatus of claim 9 , wherein the electronic mesh block is a first electronic mesh block and the output signal is a first output signal, the apparatus further comprising:
a second electronic mesh block configured to generate a second output signal, the second output signal indicating whether an unauthorized activity on the second electronic mesh block is detected, and
wherein the clock tamper detector performs the OR operation on the first and second output signals.

17. The apparatus of claim 16 , wherein the second time corresponds to a rising edge of a clock signal received by the clock tamper detector.

18. The apparatus of claim 9 , wherein the first and second pseudo-random numbers are generated using first and second linear-feedback shift registers (LFSRs), respectively,
wherein the electronic mesh block includes:
a substrate;
a device layer disposed over the substrate and including a plurality of electronic devices;
a plurality of lower interconnection layers disposed over the device layer and including a plurality of wires interconnecting the plurality of electronic devices;
an upper interconnect layer disposed over t

Assignees

• Marvell World Trade Ltd

Inventors

• A L Krishnasamy Raj Kumar
• Thum Chia Chieh
• Lee Moo Kit

Classifications

• G09C1/00 Primary

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/004

  for fault attacks · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H05K1/0275

  Security details, e.g. tampering prevention or detection · CPC title

• G06F21/86 Primary

  Secure or tamper-resistant housings · CPC title